From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 .../src/main/scala/chisel3/internal/Builder.scala  | 123 ++++++++++++++
 .../src/main/scala/chisel3/internal/Error.scala    |  91 ++++++++++
 .../main/scala/chisel3/internal/SourceInfo.scala   |  51 ++++++
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 188 +++++++++++++++++++++
 4 files changed, 453 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
 create mode 100644 chiselFrontend/src/main/scala/chisel3/internal/Error.scala
 create mode 100644 chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
 create mode 100644 chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
new file mode 100644
index 00000000..d0e28b7c
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -0,0 +1,123 @@
+// See LICENSE for license details.
+
+package Chisel.internal
+
+import scala.util.DynamicVariable
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+
+import Chisel._
+import Chisel.internal.firrtl._
+
+private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+  private var i = 0L
+  private val names = collection.mutable.HashSet[String]()
+
+  private def rename(n: String) = { i += 1; s"${n}_${i}" }
+
+  def contains(elem: String): Boolean = {
+    keywords.contains(elem) || names.contains(elem) ||
+      parent.map(_ contains elem).getOrElse(false)
+  }
+
+  def name(elem: String): String = {
+    if (this contains elem) {
+      name(rename(elem))
+    } else {
+      names += elem
+      elem
+    }
+  }
+
+  def child(kws: Set[String]): Namespace = new Namespace(Some(this), kws)
+  def child: Namespace = child(Set())
+}
+
+private[Chisel] class IdGen {
+  private var counter = -1L
+  def next: Long = {
+    counter += 1
+    counter
+  }
+}
+
+private[Chisel] trait HasId {
+  private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name
+  private[Chisel] val _parent = Builder.dynamicContext.currentModule
+  _parent.foreach(_.addId(this))
+
+  private[Chisel] val _id = Builder.idGen.next
+  override def hashCode: Int = _id.toInt
+  override def equals(that: Any): Boolean = that match {
+    case x: HasId => _id == x._id
+    case _ => false
+  }
+
+  // Facilities for 'suggesting' a name to this.
+  // Post-name hooks called to carry the suggestion to other candidates as needed
+  private var suggested_name: Option[String] = None
+  private val postname_hooks = scala.collection.mutable.ListBuffer.empty[String=>Unit]
+  // Only takes the first suggestion!
+  def suggestName(name: =>String): this.type = {
+    if(suggested_name.isEmpty) suggested_name = Some(name)
+    for(hook <- postname_hooks) { hook(name) }
+    this
+  }
+  private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+
+  // Uses a namespace to convert suggestion into a true name
+  // Will not do any naming if the reference already assigned.
+  // (e.g. tried to suggest a name to part of a Bundle)
+  private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit =
+    if(_ref.isEmpty) {
+      val candidate_name = suggested_name.getOrElse(default)
+      val available_name = namespace.name(candidate_name)
+      setRef(Ref(available_name))
+    }
+
+  private var _ref: Option[Arg] = None
+  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[Chisel] def getRef: Arg = _ref.get
+}
+
+private[Chisel] class DynamicContext {
+  val idGen = new IdGen
+  val globalNamespace = new Namespace(None, Set())
+  val components = ArrayBuffer[Component]()
+  var currentModule: Option[Module] = None
+  val errors = new ErrorLog
+}
+
+private[Chisel] object Builder {
+  // All global mutable state must be referenced via dynamicContextVar!!
+  private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
+
+  def dynamicContext: DynamicContext =
+    dynamicContextVar.value getOrElse (new DynamicContext)
+  def idGen: IdGen = dynamicContext.idGen
+  def globalNamespace: Namespace = dynamicContext.globalNamespace
+  def components: ArrayBuffer[Component] = dynamicContext.components
+
+  def pushCommand[T <: Command](c: T): T = {
+    dynamicContext.currentModule.foreach(_._commands += c)
+    c
+  }
+  def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id
+
+  def errors: ErrorLog = dynamicContext.errors
+  def error(m: => String): Unit = errors.error(m)
+
+  def build[T <: Module](f: => T): Circuit = {
+    dynamicContextVar.withValue(Some(new DynamicContext)) {
+      errors.info("Elaborating design...")
+      val mod = f
+      mod.forceName(mod.name, globalNamespace)
+      errors.checkpoint()
+      errors.info("Done elaborating.")
+
+      Circuit(components.last.name, components)
+    }
+  }
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
new file mode 100644
index 00000000..6c4c0880
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -0,0 +1,91 @@
+// See LICENSE for license details.
+
+package Chisel.internal
+
+import scala.collection.mutable.ArrayBuffer
+
+import Chisel._
+
+class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
+
+private[Chisel] object throwException {
+  def apply(s: String, t: Throwable = null): Nothing =
+    throw new ChiselException(s, t)
+}
+
+/** Records and reports runtime errors and warnings. */
+private[Chisel] class ErrorLog {
+  def hasErrors: Boolean = errors.exists(_.isFatal)
+
+  /** Log an error message */
+  def error(m: => String): Unit =
+    errors += new Error(m, getUserLineNumber)
+
+  /** Log a warning message */
+  def warning(m: => String): Unit =
+    errors += new Warning(m, getUserLineNumber)
+
+  /** Emit an informational message */
+  def info(m: String): Unit =
+    println(new Info("[%2.3f] %s".format(elapsedTime/1e3, m), None))  // scalastyle:ignore regex
+
+  /** Prints error messages generated by Chisel at runtime. */
+  def report(): Unit = errors foreach println  // scalastyle:ignore regex
+
+  /** Throw an exception if any errors have yet occurred. */
+  def checkpoint(): Unit = if(hasErrors) {
+    import Console._
+    throwException(errors.map(_ + "\n").reduce(_ + _) +
+      UNDERLINED + "CODE HAS " + errors.filter(_.isFatal).length + RESET +
+      UNDERLINED + " " + RED + "ERRORS" + RESET +
+      UNDERLINED + " and " + errors.filterNot(_.isFatal).length + RESET +
+      UNDERLINED + " " + YELLOW + "WARNINGS" + RESET)
+  }
+
+  private def findFirstUserFrame(stack: Array[StackTraceElement]): Option[StackTraceElement] = {
+    def isUserCode(ste: StackTraceElement): Boolean = {
+      def isUserModule(c: Class[_]): Boolean =
+        c != null && (c == classOf[Module] || isUserModule(c.getSuperclass))
+      isUserModule(Class.forName(ste.getClassName))
+    }
+
+    stack.indexWhere(isUserCode) match {
+      case x if x < 0 => None
+      case x => Some(stack(x))
+    }
+  }
+
+  private def getUserLineNumber =
+    findFirstUserFrame(Thread.currentThread().getStackTrace)
+
+  private val errors = ArrayBuffer[LogEntry]()
+
+  private val startTime = System.currentTimeMillis
+  private def elapsedTime: Long = System.currentTimeMillis - startTime
+}
+
+private abstract class LogEntry(msg: => String, line: Option[StackTraceElement]) {
+  def isFatal: Boolean = false
+  def format: String
+
+  override def toString: String = line match {
+    case Some(l) => s"${format} ${l.getFileName}:${l.getLineNumber}: ${msg} in class ${l.getClassName}"
+    case None => s"${format} ${msg}"
+  }
+
+  protected def tag(name: String, color: String): String =
+    s"[${color}${name}${Console.RESET}]"
+}
+
+private class Error(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
+  override def isFatal: Boolean = true
+  def format: String = tag("error", Console.RED)
+}
+
+private class Warning(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
+  def format: String = tag("warn", Console.YELLOW)
+}
+
+private class Info(msg: => String, line: Option[StackTraceElement]) extends LogEntry(msg, line) {
+  def format: String = tag("info", Console.MAGENTA)
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
new file mode 100644
index 00000000..66bfc7a4
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -0,0 +1,51 @@
+// See LICENSE for license details.
+
+// This file contains macros for adding source locators at the point of invocation.
+//
+// This is not part of coreMacros to disallow this macro from being implicitly invoked in Chisel
+// frontend (and generating source locators in Chisel core), which is almost certainly a bug.
+//
+// Note: While these functions and definitions are not private (macros can't be
+// private), these are NOT meant to be part of the public API (yet) and no
+// forward compatibility guarantees are made.
+// A future revision may stabilize the source locator API to allow library
+// writers to append source locator information at the point of a library
+// function invocation.
+
+package Chisel.internal.sourceinfo
+
+import scala.language.experimental.macros
+import scala.reflect.macros.blackbox.Context
+
+/** Abstract base class for generalized source information.
+  */
+sealed trait SourceInfo
+
+sealed trait NoSourceInfo extends SourceInfo
+
+/** For when source info can't be generated because of a technical limitation, like for Reg because
+  * Scala macros don't support named or default arguments.
+  */
+case object UnlocatableSourceInfo extends NoSourceInfo
+
+/** For when source info isn't generated because the function is deprecated and we're lazy.
+  */
+case object DeprecatedSourceInfo extends NoSourceInfo
+
+/** For FIRRTL lines from a Scala source line.
+  */
+case class SourceLine(filename: String, line: Int, col: Int) extends SourceInfo
+
+/** Provides a macro that returns the source information at the invocation point.
+  */
+object SourceInfoMacro {
+  def generate_source_info(c: Context): c.Tree = {
+    import c.universe._
+    val p = c.enclosingPosition
+    q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+  }
+}
+
+object SourceInfo {
+  implicit def materialize: SourceInfo = macro SourceInfoMacro.generate_source_info
+}
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
new file mode 100644
index 00000000..62784cee
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -0,0 +1,188 @@
+// See LICENSE for license details.
+
+package Chisel.internal.firrtl
+import Chisel._
+import Chisel.internal._
+import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+
+case class PrimOp(val name: String) {
+  override def toString: String = name
+}
+
+object PrimOp {
+  val AddOp = PrimOp("add")
+  val SubOp = PrimOp("sub")
+  val TailOp = PrimOp("tail")
+  val HeadOp = PrimOp("head")
+  val TimesOp = PrimOp("mul")
+  val DivideOp = PrimOp("div")
+  val RemOp = PrimOp("rem")
+  val ShiftLeftOp = PrimOp("shl")
+  val ShiftRightOp = PrimOp("shr")
+  val DynamicShiftLeftOp = PrimOp("dshl")
+  val DynamicShiftRightOp = PrimOp("dshr")
+  val BitAndOp = PrimOp("and")
+  val BitOrOp = PrimOp("or")
+  val BitXorOp = PrimOp("xor")
+  val BitNotOp = PrimOp("not")
+  val ConcatOp = PrimOp("cat")
+  val BitsExtractOp = PrimOp("bits")
+  val LessOp = PrimOp("lt")
+  val LessEqOp = PrimOp("leq")
+  val GreaterOp = PrimOp("gt")
+  val GreaterEqOp = PrimOp("geq")
+  val EqualOp = PrimOp("eq")
+  val PadOp = PrimOp("pad")
+  val NotEqualOp = PrimOp("neq")
+  val NegOp = PrimOp("neg")
+  val MultiplexOp = PrimOp("mux")
+  val XorReduceOp = PrimOp("xorr")
+  val ConvertOp = PrimOp("cvt")
+  val AsUIntOp = PrimOp("asUInt")
+  val AsSIntOp = PrimOp("asSInt")
+}
+
+abstract class Arg {
+  def fullName(ctx: Component): String = name
+  def name: String
+}
+
+case class Node(id: HasId) extends Arg {
+  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
+  def name: String = id.getRef.name
+}
+
+abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
+  private[Chisel] def forcedWidth = widthArg.known
+  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+
+  protected def minWidth: Int
+  if (forcedWidth) {
+    require(widthArg.get >= minWidth,
+      s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+  }
+}
+
+case class ILit(n: BigInt) extends Arg {
+  def name: String = n.toString
+}
+
+case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
+  def name: String = "UInt" + width + "(\"h0" + num.toString(16) + "\")"
+  def minWidth: Int = 1 max n.bitLength
+
+  require(n >= 0, s"UInt literal ${n} is negative")
+}
+
+case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
+  def name: String = {
+    val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
+    s"asSInt(${ULit(unsigned, width).name})"
+  }
+  def minWidth: Int = 1 + n.bitLength
+}
+
+case class Ref(name: String) extends Arg
+case class ModuleIO(mod: Module, name: String) extends Arg {
+  override def fullName(ctx: Component): String =
+    if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
+}
+case class Slot(imm: Node, name: String) extends Arg {
+  override def fullName(ctx: Component): String =
+    if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}"
+}
+case class Index(imm: Arg, value: Arg) extends Arg {
+  def name: String = s"[$value]"
+  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
+}
+
+object Width {
+  def apply(x: Int): Width = KnownWidth(x)
+  def apply(): Width = UnknownWidth()
+}
+
+sealed abstract class Width {
+  type W = Int
+  def max(that: Width): Width = this.op(that, _ max _)
+  def + (that: Width): Width = this.op(that, _ + _)
+  def + (that: Int): Width = this.op(this, (a, b) => a + that)
+  def shiftRight(that: Int): Width = this.op(this, (a, b) => 0 max (a - that))
+  def dynamicShiftLeft(that: Width): Width =
+    this.op(that, (a, b) => a + (1 << b) - 1)
+
+  def known: Boolean
+  def get: W
+  protected def op(that: Width, f: (W, W) => W): Width
+}
+
+sealed case class UnknownWidth() extends Width {
+  def known: Boolean = false
+  def get: Int = None.get
+  def op(that: Width, f: (W, W) => W): Width = this
+  override def toString: String = ""
+}
+
+sealed case class KnownWidth(value: Int) extends Width {
+  require(value >= 0)
+  def known: Boolean = true
+  def get: Int = value
+  def op(that: Width, f: (W, W) => W): Width = that match {
+    case KnownWidth(x) => KnownWidth(f(value, x))
+    case _ => that
+  }
+  override def toString: String = s"<${value.toString}>"
+}
+
+sealed abstract class MemPortDirection(name: String) {
+  override def toString: String = name
+}
+object MemPortDirection {
+  object READ extends MemPortDirection("read")
+  object WRITE extends MemPortDirection("write")
+  object RDWR extends MemPortDirection("rdwr")
+  object INFER extends MemPortDirection("infer")
+}
+
+abstract class Command {
+  def sourceInfo: SourceInfo
+}
+abstract class Definition extends Command {
+  def id: HasId
+  def name: String = id.getRef.name
+}
+case class DefPrim[T <: Data](sourceInfo: SourceInfo, id: T, op: PrimOp, args: Arg*) extends Definition
+case class DefInvalid(sourceInfo: SourceInfo, arg: Arg) extends Command
+case class DefWire(sourceInfo: SourceInfo, id: Data) extends Definition
+case class DefReg(sourceInfo: SourceInfo, id: Data, clock: Arg) extends Definition
+case class DefRegInit(sourceInfo: SourceInfo, id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition
+case class DefMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: Int) extends Definition
+case class DefSeqMemory(sourceInfo: SourceInfo, id: HasId, t: Data, size: Int) extends Definition
+case class DefMemPort[T <: Data](sourceInfo: SourceInfo, id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition
+case class DefInstance(sourceInfo: SourceInfo, id: Module, ports: Seq[Port]) extends Definition
+case class WhenBegin(sourceInfo: SourceInfo, pred: Arg) extends Command
+case class WhenEnd(sourceInfo: SourceInfo) extends Command
+case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
+case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
+case class Stop(sourceInfo: SourceInfo, clk: Arg, ret: Int) extends Command
+case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
+case class Port(id: Data, dir: Direction)
+case class Printf(sourceInfo: SourceInfo, clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
+  require(formatIn.forall(c => c.toInt > 0 && c.toInt < 128), "format strings must comprise non-null ASCII values")
+  def format: String = {
+    def escaped(x: Char) = {
+      require(x.toInt >= 0)
+      if (x == '"' || x == '\\') {
+        s"\\${x}"
+      } else if (x == '\n') {
+        "\\n"
+      } else {
+        require(x.toInt >= 32) // TODO \xNN once FIRRTL issue #59 is resolved
+        x
+      }
+    }
+    formatIn.map(escaped _).mkString
+  }
+}
+
+case class Circuit(name: String, components: Seq[Component])
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 .../src/main/scala/chisel3/internal/Builder.scala  | 54 ++++++++++++----------
 .../src/main/scala/chisel3/internal/Error.scala    |  8 ++--
 .../main/scala/chisel3/internal/SourceInfo.scala   |  4 +-
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 14 +++---
 4 files changed, 44 insertions(+), 36 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index d0e28b7c..0e0a88cc 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -1,29 +1,35 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel3.internal
 
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
-import Chisel._
-import Chisel.internal.firrtl._
+import chisel3._
+import core._
+import firrtl._
 
-private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
-  private var i = 0L
-  private val names = collection.mutable.HashSet[String]()
+private[chisel3] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+  private val names = collection.mutable.HashMap[String, Long]()
+  for (keyword <- keywords)
+    names(keyword) = 1
 
-  private def rename(n: String) = { i += 1; s"${n}_${i}" }
+  private def rename(n: String): String = {
+    val index = names.getOrElse(n, 1L)
+    val tryName = s"${n}_${index}"
+    names(n) = index + 1
+    if (this contains tryName) rename(n) else tryName
+  }
 
   def contains(elem: String): Boolean = {
-    keywords.contains(elem) || names.contains(elem) ||
-      parent.map(_ contains elem).getOrElse(false)
+    names.contains(elem) || parent.map(_ contains elem).getOrElse(false)
   }
 
   def name(elem: String): String = {
     if (this contains elem) {
       name(rename(elem))
     } else {
-      names += elem
+      names(elem) = 1
       elem
     }
   }
@@ -32,7 +38,7 @@ private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]
   def child: Namespace = child(Set())
 }
 
-private[Chisel] class IdGen {
+private[chisel3] class IdGen {
   private var counter = -1L
   def next: Long = {
     counter += 1
@@ -40,12 +46,12 @@ private[Chisel] class IdGen {
   }
 }
 
-private[Chisel] trait HasId {
-  private[Chisel] def _onModuleClose {} // scalastyle:ignore method.name
-  private[Chisel] val _parent = Builder.dynamicContext.currentModule
+private[chisel3] trait HasId {
+  private[chisel3] def _onModuleClose {} // scalastyle:ignore method.name
+  private[chisel3] val _parent = Builder.dynamicContext.currentModule
   _parent.foreach(_.addId(this))
 
-  private[Chisel] val _id = Builder.idGen.next
+  private[chisel3] val _id = Builder.idGen.next
   override def hashCode: Int = _id.toInt
   override def equals(that: Any): Boolean = that match {
     case x: HasId => _id == x._id
@@ -62,12 +68,12 @@ private[Chisel] trait HasId {
     for(hook <- postname_hooks) { hook(name) }
     this
   }
-  private[Chisel] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
+  private[chisel3] def addPostnameHook(hook: String=>Unit): Unit = postname_hooks += hook
 
   // Uses a namespace to convert suggestion into a true name
   // Will not do any naming if the reference already assigned.
   // (e.g. tried to suggest a name to part of a Bundle)
-  private[Chisel] def forceName(default: =>String, namespace: Namespace): Unit =
+  private[chisel3] def forceName(default: =>String, namespace: Namespace): Unit =
     if(_ref.isEmpty) {
       val candidate_name = suggested_name.getOrElse(default)
       val available_name = namespace.name(candidate_name)
@@ -75,14 +81,14 @@ private[Chisel] trait HasId {
     }
 
   private var _ref: Option[Arg] = None
-  private[Chisel] def setRef(imm: Arg): Unit = _ref = Some(imm)
-  private[Chisel] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
-  private[Chisel] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
-  private[Chisel] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
-  private[Chisel] def getRef: Arg = _ref.get
+  private[chisel3] def setRef(imm: Arg): Unit = _ref = Some(imm)
+  private[chisel3] def setRef(parent: HasId, name: String): Unit = setRef(Slot(Node(parent), name))
+  private[chisel3] def setRef(parent: HasId, index: Int): Unit = setRef(Index(Node(parent), ILit(index)))
+  private[chisel3] def setRef(parent: HasId, index: UInt): Unit = setRef(Index(Node(parent), index.ref))
+  private[chisel3] def getRef: Arg = _ref.get
 }
 
-private[Chisel] class DynamicContext {
+private[chisel3] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
@@ -90,7 +96,7 @@ private[Chisel] class DynamicContext {
   val errors = new ErrorLog
 }
 
-private[Chisel] object Builder {
+private[chisel3] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
 
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
index 6c4c0880..7ae0580f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Error.scala
@@ -1,20 +1,20 @@
 // See LICENSE for license details.
 
-package Chisel.internal
+package chisel3.internal
 
 import scala.collection.mutable.ArrayBuffer
 
-import Chisel._
+import chisel3.core._
 
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private[Chisel] object throwException {
+private[chisel3] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private[Chisel] class ErrorLog {
+private[chisel3] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index 66bfc7a4..5e3bf33e 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -12,7 +12,7 @@
 // writers to append source locator information at the point of a library
 // function invocation.
 
-package Chisel.internal.sourceinfo
+package chisel3.internal.sourceinfo
 
 import scala.language.experimental.macros
 import scala.reflect.macros.blackbox.Context
@@ -42,7 +42,7 @@ object SourceInfoMacro {
   def generate_source_info(c: Context): c.Tree = {
     import c.universe._
     val p = c.enclosingPosition
-    q"_root_.Chisel.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
+    q"_root_.chisel3.internal.sourceinfo.SourceLine(${p.source.file.name}, ${p.line}, ${p.column})"
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 62784cee..64d7d5fd 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -1,9 +1,11 @@
 // See LICENSE for license details.
 
-package Chisel.internal.firrtl
-import Chisel._
-import Chisel.internal._
-import Chisel.internal.sourceinfo.{SourceInfo, NoSourceInfo}
+package chisel3.internal.firrtl
+
+import chisel3._
+import core._
+import chisel3.internal._
+import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo}
 
 case class PrimOp(val name: String) {
   override def toString: String = name
@@ -53,8 +55,8 @@ case class Node(id: HasId) extends Arg {
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[Chisel] def forcedWidth = widthArg.known
-  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  private[chisel3] def forcedWidth = widthArg.known
+  private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
 
   protected def minWidth: Int
   if (forcedWidth) {
-- 
cgit v1.2.3


From 01e14c8c885527861152443f1233fa77b03cb8b5 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 16:51:21 -0700
Subject: Merge in "complete" versions of Mem, Reg.

---
 chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index e5b85736..168e19b2 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -124,7 +124,11 @@ private[chisel3] object Builder {
     forcedModule._commands += c
     c
   }
-  def pushOp[T <: Data](cmd: DefPrim[T]): T = pushCommand(cmd).id
+  def pushOp[T <: Data](cmd: DefPrim[T]): T = {
+    // Bind each element of the returned Data to being a Op
+    Binding.bind(cmd.id, OpBinder(forcedModule), "Error: During op creation, fresh result")
+    pushCommand(cmd).id
+  }
 
   def errors: ErrorLog = dynamicContext.errors
   def error(m: => String): Unit = errors.error(m)
-- 
cgit v1.2.3


From 8c8349e3eab69235f48826b59af8f67fe0b3e80c Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 12 Aug 2016 09:39:39 -0700
Subject: Add support for per-Module compilation options. Nothing uses these
 now, but when we integrate Stephen's PR200, we'll need a way to selectively
 enable some strict connection checks on a file by file basis. We plan to do
 this using package imports which will define suitable compilation options.

---
 .../src/main/scala/chisel3/internal/Builder.scala        | 11 ++++++++---
 .../src/main/scala/chisel3/internal/CompileOptions.scala | 16 ++++++++++++++++
 2 files changed, 24 insertions(+), 3 deletions(-)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index cecbd91e..68dd269c 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -97,12 +97,16 @@ private[chisel3] trait HasId {
   private[chisel3] def getRef: Arg = _ref.get
 }
 
-private[chisel3] class DynamicContext {
+private[chisel3] class DynamicContext(optionMap: Option[Map[String, String]] = None) {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
   var currentModule: Option[Module] = None
   val errors = new ErrorLog
+  val compileOptions = new CompileOptions(optionMap match {
+    case Some(map: Map[String, String]) => map
+    case None => Map[String, String]()
+  })
 }
 
 private[chisel3] object Builder {
@@ -115,6 +119,7 @@ private[chisel3] object Builder {
   def globalNamespace: Namespace = dynamicContext.globalNamespace
   def components: ArrayBuffer[Component] = dynamicContext.components
 
+  def compileOptions = dynamicContext.compileOptions
   def pushCommand[T <: Command](c: T): T = {
     dynamicContext.currentModule.foreach(_._commands += c)
     c
@@ -124,8 +129,8 @@ private[chisel3] object Builder {
   def errors: ErrorLog = dynamicContext.errors
   def error(m: => String): Unit = errors.error(m)
 
-  def build[T <: Module](f: => T): Circuit = {
-    dynamicContextVar.withValue(Some(new DynamicContext)) {
+  def build[T <: Module](f: => T, optionMap: Option[Map[String, String]] = None): Circuit = {
+    dynamicContextVar.withValue(Some(new DynamicContext(optionMap))) {
       errors.info("Elaborating design...")
       val mod = f
       mod.forceName(mod.name, globalNamespace)
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
new file mode 100644
index 00000000..12789855
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -0,0 +1,16 @@
+// See LICENSE for license details.
+
+package chisel3.internal
+
+/** Initialize compilation options from a string map.
+  *
+  * @param optionsMap the map from "option" to "value"
+  */
+class CompileOptions(optionsMap: Map[String, String]) {
+  // The default for settings related to "strictness".
+  val strictDefault: String = optionsMap.getOrElse("strict", "false")
+  // Should Bundle connections require a strict match of fields.
+  // If true and the same fields aren't present in both source and sink, a MissingFieldException,
+  // MissingLeftFieldException, or MissingRightFieldException will be thrown.
+  val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean
+}
-- 
cgit v1.2.3


From 4ab2aa0e9209000fb0ba1299ac18db2e033f708f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 12 Aug 2016 14:17:52 -0700
Subject: Use compileOptions to determine if Missing...FieldExceptions are
 thrown.

---
 chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index dddc261e..9f2b1631 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -118,6 +118,7 @@ private[chisel3] object Builder {
   def idGen: IdGen = dynamicContext.idGen
   def globalNamespace: Namespace = dynamicContext.globalNamespace
   def components: ArrayBuffer[Component] = dynamicContext.components
+  def compileOptions = dynamicContext.compileOptions
 
   def currentModule: Option[Module] = dynamicContext.currentModule
   def currentModule_=(target: Option[Module]): Unit = {
@@ -133,7 +134,6 @@ private[chisel3] object Builder {
 
   // TODO(twigg): Ideally, binding checks and new bindings would all occur here
   // However, rest of frontend can't support this yet.
-  def compileOptions = dynamicContext.compileOptions
   def pushCommand[T <: Command](c: T): T = {
     forcedModule._commands += c
     c
-- 
cgit v1.2.3


From f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 16 Aug 2016 11:59:20 -0700
Subject: Reduce rocket-chip elaboration errors.

---
 chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala | 6 ++++++
 1 file changed, 6 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
index 12789855..b809b8fe 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -9,8 +9,14 @@ package chisel3.internal
 class CompileOptions(optionsMap: Map[String, String]) {
   // The default for settings related to "strictness".
   val strictDefault: String = optionsMap.getOrElse("strict", "false")
+  val looseDefault: String = (!(strictDefault.toBoolean)).toString
   // Should Bundle connections require a strict match of fields.
   // If true and the same fields aren't present in both source and sink, a MissingFieldException,
   // MissingLeftFieldException, or MissingRightFieldException will be thrown.
   val connectFieldsMustMatch: Boolean = optionsMap.getOrElse("connectFieldsMustMatch", strictDefault).toBoolean
+  val regTypeMustBeUnbound: Boolean = optionsMap.getOrElse("regTypeMustBeUnbound", strictDefault).toBoolean
+  val autoIOWrap: Boolean = optionsMap.getOrElse("autoIOWrap", looseDefault).toBoolean
+  val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean
+  val internalConnectionToInputOk: Boolean = optionsMap.getOrElse("internalConnectionToInputOk", looseDefault).toBoolean
+  val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean
 }
-- 
cgit v1.2.3


From 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 17 Aug 2016 13:30:05 -0700
Subject: Rocket-chip updates. Assume LHSItOutput if neither side is driving.
 Restore Wire()'s removal of direction in binding.

---
 chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala | 1 +
 1 file changed, 1 insertion(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
index b809b8fe..93879950 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/CompileOptions.scala
@@ -19,4 +19,5 @@ class CompileOptions(optionsMap: Map[String, String]) {
   val portDeterminesDirection: Boolean = optionsMap.getOrElse("portDeterminesDirection", looseDefault).toBoolean
   val internalConnectionToInputOk: Boolean = optionsMap.getOrElse("internalConnectionToInputOk", looseDefault).toBoolean
   val tryConnectionsSwapped: Boolean = optionsMap.getOrElse("tryConnectionsSwapped", looseDefault).toBoolean
+  val assumeLHSIsOutput: Boolean = optionsMap.getOrElse("assumeLHSIsOutput", looseDefault).toBoolean
 }
-- 
cgit v1.2.3