From 822160cc8e76e70643fb56707bb39f6f7526b6fd Mon Sep 17 00:00:00 2001 From: jackkoenig Date: Thu, 22 Sep 2016 22:38:33 -0700 Subject: Add support for parameterized BlackBoxes Also restrict black boxes to not allow hardware inside of them since it was being silently dropped anyway. Resolves #289 --- chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 0f866c27..17b869f2 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -215,8 +215,14 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command -case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command +abstract class Component extends Arg { + def id: Module + def name: String + def ports: Seq[Port] +} +case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component]) -- cgit v1.2.3 From bb1cb894f6f1c88e0d60de1501e86d68de7c0f76 Mon Sep 17 00:00:00 2001 From: chick Date: Wed, 9 Nov 2016 15:57:06 -0800 Subject: first attack on creating a range api for chisel3 --- .../main/scala/chisel3/internal/firrtl/IR.scala | 57 ++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 17b869f2..d463d78e 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -109,6 +109,63 @@ case class Index(imm: Arg, value: Arg) extends Arg { override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]" } +object Range { + def log2Up(value: BigInt): Int = { + require(value >= 0) + 1 max (value-1).bitLength + } +} + +/*sealed abstract class Range { + +}*/ +sealed trait Bound +sealed trait NumericBound[T] extends Bound { + val value: T +} +sealed case class Open[T](value: T) extends NumericBound[T] +sealed case class Closed[T](value: T) extends NumericBound[T] + +sealed trait Range { + val min: Bound + val max: Bound + def getWidth: Width +} + +sealed trait KnownIntRange extends Range { + val min: NumericBound[Int] + val max: NumericBound[Int] + + require( (min, max) match { + case (low, Open(high_val)) => low.value < high_val + case (Open(low_val), high) => low_val < high.value + case (Closed(low_val), Closed(high_val)) => low_val <= high_val + }) +} + +sealed case class KnownUIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange { + require (min.value >= 0) + + def getWidth: Width = max match { + case Open(v) => Width(BigInt(v - 1).bitLength.max(1)) + case Closed(v) => Width(BigInt(v).bitLength.max(1)) + } +} + +sealed case class KnownSIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange { + + val maxWidth = max match { + case Open(v) => Width(BigInt(v - 1).bitLength + 1) + case Closed(v) => Width(BigInt(v).bitLength + 1) + } + val minWidth = min match { + case Open(v) => Width(BigInt(v + 1).bitLength + 1) + case Closed(v) => Width(BigInt(v).bitLength + 1) + } + def getWidth: Width = maxWidth.max(minWidth) + +} + object Width { def apply(x: Int): Width = KnownWidth(x) def apply(): Width = UnknownWidth() -- cgit v1.2.3 From 876bc32feca6bd0a2aaec7019fd3d29675ce0255 Mon Sep 17 00:00:00 2001 From: ducky Date: Wed, 16 Nov 2016 15:23:36 -0800 Subject: Fix open-open range specifier, remove dead code, restyle tests --- .../src/main/scala/chisel3/internal/firrtl/IR.scala | 15 +++------------ 1 file changed, 3 insertions(+), 12 deletions(-) (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index d463d78e..262b939f 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -109,16 +109,6 @@ case class Index(imm: Arg, value: Arg) extends Arg { override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]" } -object Range { - def log2Up(value: BigInt): Int = { - require(value >= 0) - 1 max (value-1).bitLength - } -} - -/*sealed abstract class Range { - -}*/ sealed trait Bound sealed trait NumericBound[T] extends Bound { val value: T @@ -137,8 +127,9 @@ sealed trait KnownIntRange extends Range { val max: NumericBound[Int] require( (min, max) match { - case (low, Open(high_val)) => low.value < high_val - case (Open(low_val), high) => low_val < high.value + case (Open(low_val), Open(high_val)) => low_val < high_val - 1 + case (Closed(low_val), Open(high_val)) => low_val < high_val + case (Open(low_val), Closed(high_val)) => low_val < high_val case (Closed(low_val), Closed(high_val)) => low_val <= high_val }) } -- cgit v1.2.3 From 6725dbd501e3d3a0d6a626f69473115069ac3b34 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 1 Dec 2016 17:34:39 -0800 Subject: Fix spelling of "specified". (#392) --- chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 262b939f..699cc13c 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -64,7 +64,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg { protected def minWidth: Int if (forcedWidth) { require(widthArg.get >= minWidth, - s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") + s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.") } } -- cgit v1.2.3 From ad53161bbb9f67e16b88ca7a508a537f88d77e05 Mon Sep 17 00:00:00 2001 From: Chick Markley Date: Wed, 7 Dec 2016 10:31:23 -0800 Subject: Support for creating chisel annotations that are consumed by firrtl (#393) * Support for creating chisel annotations that are consumed by firrtl Update annotation serialization in Driver Add DiamondAnnotation Spec that illustrates how to do simple annotations frontEnd must have dependency on firrtl Add annotation method to Module Circuit has extra optional parameter that is Seq of Annotations In Builder add annotation buffer to DynamicContext to store annotations created in modules Added explicit types on naming api methods to avoid type confusion Because some names are not available until elaboration create intermediate ChiselAnnotation that gets turned into a firrtl Annotation after elaboration In execute pass firrtl text and annotation to firrtl are now passed in through optionManager, though intermediate file .fir and .anno files are still created for inspection and/or later use * Somehow missed ChiselAnnotation * fixes for Jack's review of PR --- chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl') diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index 699cc13c..50400034 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -7,6 +7,8 @@ import core._ import chisel3.internal._ import chisel3.internal.sourceinfo.{SourceInfo, NoSourceInfo} +import _root_.firrtl.annotations.Annotation + case class PrimOp(val name: String) { override def toString: String = name } @@ -273,4 +275,4 @@ abstract class Component extends Arg { case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component -case class Circuit(name: String, components: Seq[Component]) +case class Circuit(name: String, components: Seq[Component], annotations: Seq[Annotation] = Seq.empty) -- cgit v1.2.3