From 9e992816e570284193e121cd9c24503fd8cb4427 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Mon, 21 Jan 2019 16:24:43 -0800
Subject: Unify internal (chisel3.core) and external (chisel3 /
 chisel3.experimental) Module class names (#994)

---
 chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index ae8b248a..c05d402d 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -286,7 +286,7 @@ abstract class Component extends Arg {
   def name: String
   def ports: Seq[Port]
 }
-case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
 case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation] = Seq.empty)
-- 
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