From 64a8f52c48905e9bf28e709cde2de89215a35c80 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 31 Jul 2018 14:11:33 -0700
Subject: Ensure names work for bundles and literals. (#853)

Fixes #852---
 .../src/main/scala/chisel3/internal/firrtl/IR.scala     | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/internal/firrtl')

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 6b555a82..b6630f7f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -53,13 +53,26 @@ abstract class Arg {
 }
 
 case class Node(id: HasId) extends Arg {
-  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
-  def name: String = id.getRef.name
+  override def fullName(ctx: Component): String = id.getOptionRef match {
+    case Some(arg) => arg.fullName(ctx)
+    case None => id.suggestedName.getOrElse("??")
+  }
+  def name: String = id.getOptionRef match {
+    case Some(arg) => arg.name
+    case None => id.suggestedName.getOrElse("??")
+  }
 }
 
 abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   private[chisel3] def forcedWidth = widthArg.known
   private[chisel3] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+  override def fullName(ctx: Component): String = name
+  // Ensure the node representing this LitArg has a ref to it and a literal binding.
+  def bindLitArg[T <: Bits](bits: T): T = {
+    bits.bind(ElementLitBinding(this))
+    bits.setRef(this)
+    bits
+  }
 
   protected def minWidth: Int
   if (forcedWidth) {
-- 
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