From d439ac0144826bb170c43ae71df9782cdd0d5749 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Fri, 21 Apr 2017 21:40:52 -0700
Subject: Remove VecLike/IndexedSeq from Mem type (#589)

---
 chiselFrontend/src/main/scala/chisel3/core/Mem.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index 006670e7..f935e4ee 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -32,7 +32,7 @@ object Mem {
   }
 }
 
-sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId with VecLike[T] {
+sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId {
   // REVIEW TODO: make accessors (static/dynamic, read/write) combinations consistent.
 
   /** Creates a read accessor into the memory with static addressing. See the
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