From d00a3fe9a3df5ce888b5c461181aadbd4a293bf3 Mon Sep 17 00:00:00 2001
From: Fabien Marteau
Date: Wed, 15 Feb 2017 10:03:18 +0100
Subject: Blackbox comments spelling correction thanks to edwardcwang

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index ce509f3a..fa81a4a5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -23,7 +23,7 @@ case class RawParam(value: String) extends Param
   *
   * @example
   * Some design require a differential input clock to clock the all design.
-  * With xilinx FPGA for example, a verilog template named IBUFDS must be
+  * With the xilinx FPGA for example, a Verilog template named IBUFDS must be
   * integrated to use differential input:
   * {{{
   *  IBUFDS #(.DIFF_TERM("TRUE"),
@@ -34,7 +34,7 @@ case class RawParam(value: String) extends Param
   *  );
   * }}}
   *
-  * To instanciate it, a BlackBox can be used like following:
+  * To instantiate it, a BlackBox can be used like following:
   * {{{
   * import chisel3._
   * import chisel3.experimental._
-- 
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