From 8e683de37bf92674f85a20b679f4cf64bcbe4dd7 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Thu, 17 Jan 2019 14:38:47 -0800
Subject: Fix width-inference description of Bits.<<

---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index bf1f7f63..bbe6f7e2 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -323,7 +323,7 @@ sealed abstract class Bits(private[chisel3] val width: Width) extends Element wi
     *
     * @param that a hardware component
     * @return this $coll dynamically shifted left by `that` many places, shifting in zeros from the right
-    * @note The width of the returned $coll is `width of this + pow(2, width of that)`.
+    * @note The width of the returned $coll is `width of this + pow(2, width of that) - 1`.
     * @group Bitwise
     */
   final def << (that: UInt): Bits = macro SourceInfoWhiteboxTransform.thatArg
-- 
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