From 73bb640bed2af97956515eaae18fcf54ae8485e3 Mon Sep 17 00:00:00 2001
From: Fabien Marteau
Date: Thu, 5 Jan 2017 09:50:00 +0100
Subject: BlackBox documentation: adding the verilog template to generate

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 13 +++++++++++++
 1 file changed, 13 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index fc659ded..ce509f3a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -22,6 +22,19 @@ case class RawParam(value: String) extends Param
   * to RTL modules defined outside Chisel.
   *
   * @example
+  * Some design require a differential input clock to clock the all design.
+  * With xilinx FPGA for example, a verilog template named IBUFDS must be
+  * integrated to use differential input:
+  * {{{
+  *  IBUFDS #(.DIFF_TERM("TRUE"),
+  *           .IOSTANDARD("DEFAULT")) ibufds (
+  *   .IB(ibufds_IB),
+  *   .I(ibufds_I),
+  *   .O(ibufds_O)
+  *  );
+  * }}}
+  *
+  * To instanciate it, a BlackBox can be used like following:
   * {{{
   * import chisel3._
   * import chisel3.experimental._
-- 
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