From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 13:45:05 -0700
Subject: Rename CompileOptions implicit objects.

---
 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala | 2 +-
 chiselFrontend/src/main/scala/chisel3/core/Module.scala   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index a9f89cbc..7b0cf3f7 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -5,7 +5,7 @@ package chisel3.core
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
 import chisel3.internal.sourceinfo.SourceInfo
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 47003df0..2cfc6c6a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
-- 
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