From f75366ce5c9d6c676f27aa7980637cb118a520bd Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 3 Jul 2018 18:04:47 -0600
Subject: Fix strict namer

---
 chiselFrontend/src/main/scala/chisel3/core/UserModule.scala | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/UserModule.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
index 422760ec..5183f860 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -72,11 +72,13 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions)
     for (id <- getIds) {
       id match {
         case id: BaseModule => id.forceName(default=id.desiredName, _namespace)
-        case id: Data => id.topBinding match {
+        case id: MemBase[_] => id.forceName(default="_T", _namespace)
+        case id: Data if id.topBindingOpt.isDefined => id.topBinding match {
           case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) =>
             id.forceName(default="_T", _namespace)
-          case _ =>
+          case _ =>  // don't name literals
         }
+        case id: Data if id.topBindingOpt.isEmpty =>  // don't name unbound types
       }
       id._onModuleClose
     }
-- 
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