From e27657118ff5915b96f8e3a467d464245fe09769 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Dec 2017 15:54:25 -0800
Subject: Add compileOptions to Module.apply, use for invalidating submod ports
 (#747)

Fixes #746
Also add test for https://github.com/freechipsproject/firrtl/issues/705
---
 .../src/main/scala/chisel3/core/UserModule.scala   | 23 ++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/UserModule.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
index c99d53cf..9c923037 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala
@@ -81,8 +81,15 @@ abstract class UserModule(implicit moduleCompileOptions: CompileOptions)
     component
   }
 
-  // There is no initialization to be done by default.
-  private[core] def initializeInParent() {}
+  private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
+    implicit val sourceInfo = UnlocatableSourceInfo
+
+    if (!parentCompileOptions.explicitInvalidate) {
+      for (port <- getModulePorts) {
+        pushCommand(DefInvalid(sourceInfo, port.ref))
+      }
+    }
+  }
 }
 
 /** Abstract base class for Modules, which behave much like Verilog modules.
@@ -100,14 +107,10 @@ abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions)
   // Setup ClockAndReset
   Builder.currentClockAndReset = Some(ClockAndReset(clock, reset))
 
-  private[core] override def initializeInParent() {
+  private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    if (!compileOptions.explicitInvalidate) {
-      for (port <- getModulePorts) {
-        pushCommand(DefInvalid(sourceInfo, port.ref))
-      }
-    }
+    super.initializeInParent(parentCompileOptions)
     clock := Builder.forcedClock
     reset := Builder.forcedReset
   }
@@ -173,12 +176,12 @@ abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions)
     super.generateComponent()
   }
 
-  private[core] override def initializeInParent() {
+  private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = {
     // Don't generate source info referencing parents inside a module, since this interferes with
     // module de-duplication in FIRRTL emission.
     implicit val sourceInfo = UnlocatableSourceInfo
 
-    if (!compileOptions.explicitInvalidate) {
+    if (!parentCompileOptions.explicitInvalidate) {
       pushCommand(DefInvalid(sourceInfo, io.ref))
     }
 
-- 
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