From 1fa57cc3f76bc3e5de7e6b943abe70becdcb2295 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 20 Jul 2016 17:08:55 -0700
Subject: More literal/width rangling.

---
 chiselFrontend/src/main/scala/chisel3/core/Reg.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Reg.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
index b46b96ef..e0607520 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Reg.scala
@@ -11,7 +11,7 @@ object Reg {
   private[core] def makeType[T <: Data](t: T = null, next: T = null,
 init: T = null): T = {
     if (t ne null) {
-      Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using newType?")
+      Binding.checkUnbound(t, s"t ($t) must be unbound Type. Try using cloneType?")
       t.cloneType
     } else if (next ne null) {
       next.cloneTypeWidth(Width())
-- 
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