From d408d73a171535bd7c2ba9d0037c194022b8a62f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 20 Jun 2016 11:08:46 -0700
Subject: Rename chisel3 package.

---
 .../src/main/scala/chisel3/core/Module.scala       | 119 +++++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/Module.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
new file mode 100644
index 00000000..1de3efe5
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -0,0 +1,119 @@
+// See LICENSE for license details.
+
+package chisel.core
+
+import scala.collection.mutable.{ArrayBuffer, HashSet}
+import scala.language.experimental.macros
+
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.Builder.dynamicContext
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+
+object Module {
+  /** A wrapper method that all Module instantiations must be wrapped in
+    * (necessary to help Chisel track internal state).
+    *
+    * @param m the Module being created
+    *
+    * @return the input module `m` with Chisel metadata properly set
+    */
+  def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T]
+
+  def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = {
+    // Don't generate source info referencing parents inside a module, sincce this interferes with
+    // module de-duplication in FIRRTL emission.
+    val childSourceInfo = UnlocatableSourceInfo
+
+    val parent = dynamicContext.currentModule
+    val m = bc.setRefs()
+    m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
+    dynamicContext.currentModule = parent
+    val ports = m.computePorts
+    Builder.components += Component(m, m.name, ports, m._commands)
+    pushCommand(DefInstance(sourceInfo, m, ports))
+    m.setupInParent(childSourceInfo)
+  }
+}
+
+/** Abstract base class for Modules, which behave much like Verilog modules.
+  * These may contain both logic and state which are written in the Module
+  * body (constructor).
+  *
+  * @note Module instantiations must be wrapped in a Module() call.
+  */
+abstract class Module(
+  override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
+extends HasId {
+  // _clock and _reset can be clock and reset in these 2ary constructors
+  // once chisel2 compatibility issues are resolved
+  def this(_clock: Clock) = this(Option(_clock), None)
+  def this(_reset: Bool)  = this(None, Option(_reset))
+  def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
+
+  private[core] val _namespace = Builder.globalNamespace.child
+  private[chisel] val _commands = ArrayBuffer[Command]()
+  private[core] val _ids = ArrayBuffer[HasId]()
+  dynamicContext.currentModule = Some(this)
+
+  /** Name of the instance. */
+  val name = Builder.globalNamespace.name(getClass.getName.split('.').last)
+
+  /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
+    * connections in and out of a Module may only go through `io` elements.
+    */
+  def io: Bundle
+  val clock = Clock(INPUT)
+  val reset = Bool(INPUT)
+
+  private[chisel] def addId(d: HasId) { _ids += d }
+
+  private[core] def ports: Seq[(String,Data)] = Vector(
+    ("clk", clock), ("reset", reset), ("io", io)
+  )
+
+  private[core] def computePorts = for((name, port) <- ports) yield {
+    val bundleDir = if (port.isFlip) INPUT else OUTPUT
+    Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
+  }
+
+  private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+    _parent match {
+      case Some(p) => {
+        pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
+        clock := override_clock.getOrElse(p.clock)
+        reset := override_reset.getOrElse(p.reset)
+        this
+      }
+      case None => this
+    }
+  }
+
+  private[core] def setRefs(): this.type = {
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+
+    // Suggest names to nodes using runtime reflection
+    val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*)
+    def isPublicVal(m: java.lang.reflect.Method) =
+      m.getParameterTypes.isEmpty && valNames.contains(m.getName)
+    val methods = getClass.getMethods.sortWith(_.getName > _.getName)
+    for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
+      case (id: HasId) => id.suggestName(m.getName)
+      case _ =>
+    }
+
+    // For Module instances we haven't named, suggest the name of the Module
+    _ids foreach {
+      case m: Module => m.suggestName(m.name)
+      case _ =>
+    }
+
+    // All suggestions are in, force names to every node.
+    _ids.foreach(_.forceName(default="T", _namespace))
+    _ids.foreach(_._onModuleClose)
+    this
+  }
+}
-- 
cgit v1.2.3


From 3026dd214f3db3308eaf8f876d0fc03f75c577d3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 20 Jun 2016 11:38:26 -0700
Subject: Rename "package", "import", and explicit references to "chisel3".

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 1de3efe5..7032e762 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -1,15 +1,15 @@
 // See LICENSE for license details.
 
-package chisel.core
+package chisel3.core
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
 
-import chisel.internal._
-import chisel.internal.Builder.pushCommand
-import chisel.internal.Builder.dynamicContext
-import chisel.internal.firrtl._
-import chisel.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.firrtl._
+import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -53,7 +53,7 @@ extends HasId {
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
   private[core] val _namespace = Builder.globalNamespace.child
-  private[chisel] val _commands = ArrayBuffer[Command]()
+  private[chisel3] val _commands = ArrayBuffer[Command]()
   private[core] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
@@ -67,7 +67,7 @@ extends HasId {
   val clock = Clock(INPUT)
   val reset = Bool(INPUT)
 
-  private[chisel] def addId(d: HasId) { _ids += d }
+  private[chisel3] def addId(d: HasId) { _ids += d }
 
   private[core] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
-- 
cgit v1.2.3


From 378edecbf797f19cf26f5a4d6a3ed3df701ba66d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Fri, 1 Jul 2016 11:54:49 -0700
Subject: Reflectively name Module fields declared in superclasses

Closes #229

h/t @sdtwigg @davidbiancolin
---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 7032e762..cde7032d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -2,7 +2,7 @@
 
 package chisel3.core
 
-import scala.collection.mutable.{ArrayBuffer, HashSet}
+import scala.collection.mutable.ArrayBuffer
 import scala.language.experimental.macros
 
 import chisel3.internal._
@@ -96,7 +96,11 @@ extends HasId {
     }
 
     // Suggest names to nodes using runtime reflection
-    val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*)
+    def getValNames(c: Class[_]): Set[String] = {
+      if (c == classOf[Module]) Set()
+      else getValNames(c.getSuperclass) ++ c.getDeclaredFields.map(_.getName)
+    }
+    val valNames = getValNames(this.getClass)
     def isPublicVal(m: java.lang.reflect.Method) =
       m.getParameterTypes.isEmpty && valNames.contains(m.getName)
     val methods = getClass.getMethods.sortWith(_.getName > _.getName)
-- 
cgit v1.2.3


From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 .../src/main/scala/chisel3/core/Module.scala       | 119 +++++++++++++++++++++
 1 file changed, 119 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/Module.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
new file mode 100644
index 00000000..e2101538
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -0,0 +1,119 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import scala.collection.mutable.{ArrayBuffer, HashSet}
+import scala.language.experimental.macros
+
+import internal._
+import internal.Builder.pushCommand
+import internal.Builder.dynamicContext
+import internal.firrtl._
+import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+
+object Module {
+  /** A wrapper method that all Module instantiations must be wrapped in
+    * (necessary to help Chisel track internal state).
+    *
+    * @param m the Module being created
+    *
+    * @return the input module `m` with Chisel metadata properly set
+    */
+  def apply[T <: Module](bc: => T): T = macro InstTransform.apply[T]
+
+  def do_apply[T <: Module](bc: => T)(implicit sourceInfo: SourceInfo): T = {
+    // Don't generate source info referencing parents inside a module, sincce this interferes with
+    // module de-duplication in FIRRTL emission.
+    val childSourceInfo = UnlocatableSourceInfo
+
+    val parent = dynamicContext.currentModule
+    val m = bc.setRefs()
+    m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
+    dynamicContext.currentModule = parent
+    val ports = m.computePorts
+    Builder.components += Component(m, m.name, ports, m._commands)
+    pushCommand(DefInstance(sourceInfo, m, ports))
+    m.setupInParent(childSourceInfo)
+  }
+}
+
+/** Abstract base class for Modules, which behave much like Verilog modules.
+  * These may contain both logic and state which are written in the Module
+  * body (constructor).
+  *
+  * @note Module instantiations must be wrapped in a Module() call.
+  */
+abstract class Module(
+  override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
+extends HasId {
+  // _clock and _reset can be clock and reset in these 2ary constructors
+  // once chisel2 compatibility issues are resolved
+  def this(_clock: Clock) = this(Option(_clock), None)
+  def this(_reset: Bool)  = this(None, Option(_reset))
+  def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
+
+  private[Chisel] val _namespace = Builder.globalNamespace.child
+  private[Chisel] val _commands = ArrayBuffer[Command]()
+  private[Chisel] val _ids = ArrayBuffer[HasId]()
+  dynamicContext.currentModule = Some(this)
+
+  /** Name of the instance. */
+  val name = Builder.globalNamespace.name(getClass.getName.split('.').last)
+
+  /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
+    * connections in and out of a Module may only go through `io` elements.
+    */
+  def io: Bundle
+  val clock = Clock(INPUT)
+  val reset = Bool(INPUT)
+
+  private[Chisel] def addId(d: HasId) { _ids += d }
+
+  private[Chisel] def ports: Seq[(String,Data)] = Vector(
+    ("clk", clock), ("reset", reset), ("io", io)
+  )
+
+  private[Chisel] def computePorts = for((name, port) <- ports) yield {
+    val bundleDir = if (port.isFlip) INPUT else OUTPUT
+    Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
+  }
+
+  private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+    _parent match {
+      case Some(p) => {
+        pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
+        clock := override_clock.getOrElse(p.clock)
+        reset := override_reset.getOrElse(p.reset)
+        this
+      }
+      case None => this
+    }
+  }
+
+  private[Chisel] def setRefs(): this.type = {
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+
+    // Suggest names to nodes using runtime reflection
+    val valNames = HashSet[String](getClass.getDeclaredFields.map(_.getName):_*)
+    def isPublicVal(m: java.lang.reflect.Method) =
+      m.getParameterTypes.isEmpty && valNames.contains(m.getName)
+    val methods = getClass.getMethods.sortWith(_.getName > _.getName)
+    for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
+      case (id: HasId) => id.suggestName(m.getName)
+      case _ =>
+    }
+
+    // For Module instances we haven't named, suggest the name of the Module
+    _ids foreach {
+      case m: Module => m.suggestName(m.name)
+      case _ =>
+    }
+
+    // All suggestions are in, force names to every node.
+    _ids.foreach(_.forceName(default="T", _namespace))
+    _ids.foreach(_._onModuleClose)
+    this
+  }
+}
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 .../src/main/scala/chisel3/core/Module.scala       | 29 +++++++++++-----------
 1 file changed, 15 insertions(+), 14 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index e2101538..5d510112 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -1,15 +1,16 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
 import scala.collection.mutable.{ArrayBuffer, HashSet}
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.Builder.dynamicContext
-import internal.firrtl._
-import internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel3.internal._
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.firrtl._
+import chisel3.internal.firrtl.{Command, Component, DefInstance, DefInvalid, ModuleIO}
+import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -52,9 +53,9 @@ extends HasId {
   def this(_reset: Bool)  = this(None, Option(_reset))
   def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
 
-  private[Chisel] val _namespace = Builder.globalNamespace.child
-  private[Chisel] val _commands = ArrayBuffer[Command]()
-  private[Chisel] val _ids = ArrayBuffer[HasId]()
+  private[core] val _namespace = Builder.globalNamespace.child
+  private[chisel3] val _commands = ArrayBuffer[Command]()
+  private[core] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
   /** Name of the instance. */
@@ -67,18 +68,18 @@ extends HasId {
   val clock = Clock(INPUT)
   val reset = Bool(INPUT)
 
-  private[Chisel] def addId(d: HasId) { _ids += d }
+  private[chisel3] def addId(d: HasId) { _ids += d }
 
-  private[Chisel] def ports: Seq[(String,Data)] = Vector(
+  private[core] def ports: Seq[(String,Data)] = Vector(
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[Chisel] def computePorts = for((name, port) <- ports) yield {
+  private[core] def computePorts = for((name, port) <- ports) yield {
     val bundleDir = if (port.isFlip) INPUT else OUTPUT
     Port(port, if (port.dir == NO_DIR) bundleDir else port.dir)
   }
 
-  private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
+  private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
       case Some(p) => {
         pushCommand(DefInvalid(sourceInfo, io.ref)) // init instance inputs
@@ -90,7 +91,7 @@ extends HasId {
     }
   }
 
-  private[Chisel] def setRefs(): this.type = {
+  private[core] def setRefs(): this.type = {
     for ((name, port) <- ports) {
       port.setRef(ModuleIO(this, _namespace.name(name)))
     }
-- 
cgit v1.2.3


From 3120eefc8a73b5ab3d8f909445a3e004b5e60cc6 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 19 Jul 2016 15:08:22 -0700
Subject: Incorporate connection logic. Compiles but fails tests.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 40102cd6..e8474e39 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -91,7 +91,7 @@ extends HasId {
 
   private[core] val _namespace = Builder.globalNamespace.child
   private[chisel3] val _commands = ArrayBuffer[Command]()
-  private[code] val _ids = ArrayBuffer[HasId]()
+  private[core] val _ids = ArrayBuffer[HasId]()
   Builder.currentModule = Some(this)
 
   /** Name of the instance. */
-- 
cgit v1.2.3


From 54cd58cbb435170dd2ed67dafe1cb1d769a799e8 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 20 Jul 2016 13:33:23 -0700
Subject: Generate better names for nodes (#190)

For Chisel nodes defined in Module class-level values of type Option or
Iterable, we can still use reflection to assign names based on the name
of the value. This works for arbitrary nesting of Option and Iterable so
long as the innermost type is HasId. Note that this excludes Maps which
always have an innermost type of Tuple2[_,_].
---
 .../src/main/scala/chisel3/core/Module.scala       | 24 +++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index cde7032d..ca91c5f8 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -103,10 +103,28 @@ extends HasId {
     val valNames = getValNames(this.getClass)
     def isPublicVal(m: java.lang.reflect.Method) =
       m.getParameterTypes.isEmpty && valNames.contains(m.getName)
+
+    /** Recursively suggests names to supported "container" classes
+      * Arbitrary nestings of supported classes are allowed so long as the
+      * innermost element is of type HasId
+      * Currently supported:
+      *   - Iterable
+      *   - Option
+      * (Note that Map is Iterable[Tuple2[_,_]] and thus excluded)
+      */
+    def nameRecursively(prefix: String, nameMe: Any): Unit =
+      nameMe match {
+        case (id: HasId) => id.suggestName(prefix)
+        case Some(elt) => nameRecursively(prefix, elt)
+        case (iter: Iterable[_]) if iter.hasDefiniteSize =>
+          for ((elt, i) <- iter.zipWithIndex) {
+            nameRecursively(s"${prefix}_${i}", elt)
+          }
+        case _ => // Do nothing
+      }
     val methods = getClass.getMethods.sortWith(_.getName > _.getName)
-    for (m <- methods; if isPublicVal(m)) m.invoke(this) match {
-      case (id: HasId) => id.suggestName(m.getName)
-      case _ =>
+    for (m <- methods if isPublicVal(m)) {
+      nameRecursively(m.getName, m.invoke(this))
     }
 
     // For Module instances we haven't named, suggest the name of the Module
-- 
cgit v1.2.3


From e065416d59871d790cca9d75dc9a40fcc7b52015 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Jul 2016 09:13:45 -0700
Subject: Additional compatibility code.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index a593f539..ba0720a4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -178,4 +178,6 @@ extends HasId {
     _ids.foreach(_._onModuleClose)
     this
   }
+  // For debuggers/testers
+  lazy val getPorts = computePorts
 }
-- 
cgit v1.2.3


From 2a074c828ddd8e6c20fa21d618664d50120f3d7a Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Sun, 7 Aug 2016 17:11:24 -0700
Subject: Support Module name overrides with "override def desiredName"

The API allowed this before, but not safely, as users could create
name conflicts.  This exposes the pre-deduplication/sanitization
naming API, and closes the other one.
---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index ca91c5f8..5af744c4 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -57,8 +57,11 @@ extends HasId {
   private[core] val _ids = ArrayBuffer[HasId]()
   dynamicContext.currentModule = Some(this)
 
-  /** Name of the instance. */
-  val name = Builder.globalNamespace.name(getClass.getName.split('.').last)
+  /** Desired name of this module. */
+  def desiredName = this.getClass.getName.split('.').last
+
+  /** Legalized name of this module. */
+  final val name = Builder.globalNamespace.name(desiredName)
 
   /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
     * connections in and out of a Module may only go through `io` elements.
-- 
cgit v1.2.3


From e1e7c7ea3359df1351ba979287b62458e411e846 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 8 Aug 2016 16:54:05 -0700
Subject: Provide public SignalID trait to be used to conjure up a signal
 identifier.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 5af744c4..4f25515b 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -63,6 +63,9 @@ extends HasId {
   /** Legalized name of this module. */
   final val name = Builder.globalNamespace.name(desiredName)
 
+  /** Signal name (for simulation). */
+  override def signalName(component: Component) = name
+
   /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
     * connections in and out of a Module may only go through `io` elements.
     */
-- 
cgit v1.2.3


From f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 16 Aug 2016 11:59:20 -0700
Subject: Reduce rocket-chip elaboration errors.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index bbed4d9f..450f5b58 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -4,13 +4,11 @@ package chisel3.core
 
 import scala.collection.mutable.ArrayBuffer
 import scala.language.experimental.macros
-
 import chisel3.internal._
-import chisel3.internal.Builder.pushCommand
-import chisel3.internal.Builder.dynamicContext
+import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
-import chisel3.internal.firrtl.{Command, Component, DefInstance, DefInvalid, ModuleIO}
-import chisel3.internal.sourceinfo.{SourceInfo, InstTransform, UnlocatableSourceInfo}
+import chisel3.internal.firrtl.{Command => _, _}
+import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -65,7 +63,7 @@ extends HasId {
     iodef
   }
 
-  private[this] var ioDefined: Boolean = false
+  private[core] var ioDefined: Boolean = false
 
   /**
    * This must wrap the datatype used to set the io field of any Module.
@@ -115,6 +113,10 @@ extends HasId {
 
   private[core] def computePorts: Seq[firrtl.Port] =
     for((name, port) <- ports) yield {
+      // If we're auto-wrapping IO definitions, do so now.
+      if (compileOptions.autoIOWrap && name == "io" && !ioDefined) {
+        IO(port)
+      }
       // Port definitions need to know input or output at top-level.
       // By FIRRTL semantics, 'flipped' becomes an Input
       val direction = if(Data.isFlipped(port)) Direction.Input else Direction.Output
-- 
cgit v1.2.3


From bd6e69c19aef76b6e87f7e328e03d1b93f8a1472 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 18 Aug 2016 13:42:24 -0700
Subject: Use isFirrtlFlipped() to determine port direction.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 450f5b58..24dabcbe 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -119,7 +119,7 @@ extends HasId {
       }
       // Port definitions need to know input or output at top-level.
       // By FIRRTL semantics, 'flipped' becomes an Input
-      val direction = if(Data.isFlipped(port)) Direction.Input else Direction.Output
+      val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output
       firrtl.Port(port, direction)
     }
 
-- 
cgit v1.2.3


From 119e6c7bb9096bbd163a439de09d4932303d0140 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 19 Aug 2016 12:02:10 -0700
Subject: Simplify autioIOWrap code in computePorts(). As a side-effect, handle
 BlackBoxes correctly.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 13 +++++++------
 1 file changed, 7 insertions(+), 6 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 24dabcbe..19063664 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -111,17 +111,18 @@ extends HasId {
     ("clk", clock), ("reset", reset), ("io", io)
   )
 
-  private[core] def computePorts: Seq[firrtl.Port] =
-    for((name, port) <- ports) yield {
-      // If we're auto-wrapping IO definitions, do so now.
-      if (compileOptions.autoIOWrap && name == "io" && !ioDefined) {
-        IO(port)
-      }
+  private[core] def computePorts: Seq[firrtl.Port] = {
+    // If we're auto-wrapping IO definitions, do so now.
+    if (compileOptions.autoIOWrap && !ioDefined) {
+      IO(io)
+    }
+    for ((name, port) <- ports) yield {
       // Port definitions need to know input or output at top-level.
       // By FIRRTL semantics, 'flipped' becomes an Input
       val direction = if(Data.isFirrtlFlipped(port)) Direction.Input else Direction.Output
       firrtl.Port(port, direction)
     }
+  }
 
   private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = {
     _parent match {
-- 
cgit v1.2.3


From 2d01fdf6f26f480cb7ed19c1365f181ea717ddc2 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Mon, 15 Aug 2016 18:03:12 -0700
Subject: provides signal name methods for firrtl annotation and chisel testers

* signalName: returns the chirrtl name of the signal

* pathName: returns the full path name of the signal from the top module

* parentPathName: returns the full path of the signal's parent module instance from the top module

* parentModName: returns the signal's parent **module(not instance)** name.
---
 .../src/main/scala/chisel3/core/Module.scala       | 22 ++++++++++++++++++++--
 1 file changed, 20 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 4f25515b..eb48a14d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -31,7 +31,9 @@ object Module {
     m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
     dynamicContext.currentModule = parent
     val ports = m.computePorts
-    Builder.components += Component(m, m.name, ports, m._commands)
+    val component = Component(m, m.name, ports, m._commands)
+    m._component = Some(component)
+    Builder.components += component
     pushCommand(DefInstance(sourceInfo, m, ports))
     m.setupInParent(childSourceInfo)
   }
@@ -63,8 +65,24 @@ extends HasId {
   /** Legalized name of this module. */
   final val name = Builder.globalNamespace.name(desiredName)
 
+  /** FIRRTL Module name */
+  private var _modName: Option[String] = None
+  private[chisel3] def setModName(name: String) = _modName = Some(name)
+  def modName = _modName match {
+    case Some(name) => name
+    case None => throwException("modName should be called after circuit elaboration")
+  }
+
+  /** Keep component for signal names */
+  private[chisel3] var _component: Option[Component] = None
+
+
   /** Signal name (for simulation). */
-  override def signalName(component: Component) = name
+  override def signalName =
+    if (_parent == None) name else _component match {
+      case None => getRef.name
+      case Some(c) => getRef fullName c
+    }
 
   /** IO for this Module. At the Scala level (pre-FIRRTL transformations),
     * connections in and out of a Module may only go through `io` elements.
-- 
cgit v1.2.3


From f5e9a6c6e55ba19a7c1f2353d0207189062db1c9 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 24 Aug 2016 17:09:41 -0700
Subject: Per Chisel meeting. signalName -> instanceName SignalId -> InstanceId
 Based on Stephen's comments on PR

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index eb48a14d..2426ae78 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -78,7 +78,7 @@ extends HasId {
 
 
   /** Signal name (for simulation). */
-  override def signalName =
+  override def instanceName =
     if (_parent == None) name else _component match {
       case None => getRef.name
       case Some(c) => getRef fullName c
-- 
cgit v1.2.3


From 5fcdd12fe92bd22f9cdfb8f5e39e510684b709bf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 09:33:51 -0700
Subject: Rename individual compile options. Stricter values are "true".
 Current default (not strict) values are "false".

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 19063664..b4659a52 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -113,7 +113,7 @@ extends HasId {
 
   private[core] def computePorts: Seq[firrtl.Port] = {
     // If we're auto-wrapping IO definitions, do so now.
-    if (compileOptions.autoIOWrap && !ioDefined) {
+    if (!(compileOptions.requireIOWrap || ioDefined)) {
       IO(io)
     }
     for ((name, port) <- ports) yield {
-- 
cgit v1.2.3


From 6df3a785f8abe706838bc5b4b35c3374b6512f96 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 12:17:48 -0700
Subject: Pass compileOptions as an implicit Module parameter.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index b4659a52..47003df0 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,6 +9,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
+import chisel3.NotStrict.NotStrictCompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -49,6 +50,7 @@ object Module {
   */
 abstract class Module(
   override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
+                     (implicit moduleCompileOptions: ExplicitCompileOptions)
 extends HasId {
   // _clock and _reset can be clock and reset in these 2ary constructors
   // once chisel2 compatibility issues are resolved
@@ -186,4 +188,5 @@ extends HasId {
   }
   // For debuggers/testers
   lazy val getPorts = computePorts
+  val compileOptions = moduleCompileOptions
 }
-- 
cgit v1.2.3


From 62817134d222747f1eab34626fe7b1bb13b9f6df Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 13:45:05 -0700
Subject: Rename CompileOptions implicit objects.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 47003df0..2cfc6c6a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-import chisel3.NotStrict.NotStrictCompileOptions
+import chisel3.NotStrict.CompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
-- 
cgit v1.2.3


From a2cb95bfe9e9c30b73284e97048fa0187ab0ee1d Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 21 Sep 2016 12:44:36 -0700
Subject: Make implicit clock name consistent (#288)

In the Chisel frontend, the implicit clock is named clock, but in the
generated FIRRTL, it is named clk.  There is no reason for this
discrepancy, and yet fixing it is painful, as it will break test harnesses.
Better to take the pain now than later.

Resolves #258.---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 2426ae78..8093babc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -94,7 +94,7 @@ extends HasId {
   private[chisel3] def addId(d: HasId) { _ids += d }
 
   private[core] def ports: Seq[(String,Data)] = Vector(
-    ("clk", clock), ("reset", reset), ("io", io)
+    ("clock", clock), ("reset", reset), ("io", io)
   )
 
   private[core] def computePorts = for((name, port) <- ports) yield {
-- 
cgit v1.2.3


From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 03e4f1b7..f4b36888 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-import chisel3.NotStrict.CompileOptions
+import chisel3.ImplicitCompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -51,7 +51,7 @@ object Module {
   */
 abstract class Module(
   override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
-                     (implicit moduleCompileOptions: ExplicitCompileOptions)
+                     (implicit moduleCompileOptions: ImplicitCompileOptions)
 extends HasId {
   // _clock and _reset can be clock and reset in these 2ary constructors
   // once chisel2 compatibility issues are resolved
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index f4b36888..55ef7491 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,7 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-import chisel3.ImplicitCompileOptions
+//import chisel3.CompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
@@ -51,7 +51,7 @@ object Module {
   */
 abstract class Module(
   override_clock: Option[Clock]=None, override_reset: Option[Bool]=None)
-                     (implicit moduleCompileOptions: ImplicitCompileOptions)
+                     (implicit moduleCompileOptions: CompileOptions)
 extends HasId {
   // _clock and _reset can be clock and reset in these 2ary constructors
   // once chisel2 compatibility issues are resolved
-- 
cgit v1.2.3


From 398edafd809c3abda751432c51a07b6b1158ecbd Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 15:43:34 -0700
Subject: Manual dead code elimination.

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 1 -
 1 file changed, 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 55ef7491..6fb6d036 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -9,7 +9,6 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.internal.firrtl.{Command => _, _}
 import chisel3.internal.sourceinfo.{InstTransform, SourceInfo, UnlocatableSourceInfo}
-//import chisel3.CompileOptions
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
-- 
cgit v1.2.3


From 095fd80cc1250f5ec242fde6ccc9271665f784b2 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 4 Oct 2016 11:46:13 -0700
Subject: Add CompileOptions implicits to all Module constructors - fix #310.
 (#311)

---
 chiselFrontend/src/main/scala/chisel3/core/Module.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Module.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 6fb6d036..55522b4a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -54,9 +54,9 @@ abstract class Module(
 extends HasId {
   // _clock and _reset can be clock and reset in these 2ary constructors
   // once chisel2 compatibility issues are resolved
-  def this(_clock: Clock) = this(Option(_clock), None)
-  def this(_reset: Bool)  = this(None, Option(_reset))
-  def this(_clock: Clock, _reset: Bool) = this(Option(_clock), Option(_reset))
+  def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions)
+  def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions)  = this(None, Option(_reset))(moduleCompileOptions)
+  def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions)
 
   // This function binds the iodef as a port in the hardware graph
   private[chisel3] def Port[T<:Data](iodef: T): iodef.type = {
-- 
cgit v1.2.3