From dafdeab614a5106dac4d80e147fdbc2770053e1b Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 3 Oct 2018 16:15:37 -0700
Subject: Add DataMirror.modulePorts (#901)

---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index cab6075e..869e22fb 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -87,6 +87,10 @@ object DataMirror {
     target.direction
   }
 
+  // TODO: maybe move to something like Driver or DriverUtils, since this is mainly for interacting
+  // with compiled artifacts (vs. elaboration-time reflection)?
+  def modulePorts(target: BaseModule): Seq[(String, Data)] = target.getChiselPorts
+
   // Internal reflection-style APIs, subject to change and removal whenever.
   object internal {
     def isSynthesizable(target: Data) = target.topBindingOpt.isDefined
-- 
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