From 6e12ed9fd7a771eb30f44b8e1c4ab33f6ad8e0a6 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 17 Aug 2017 17:24:02 -0700
Subject: More of the bindings refactor (#635)

Rest of the binding refactor
---
 .../src/main/scala/chisel3/core/Data.scala         | 48 +++++++++++++---------
 1 file changed, 28 insertions(+), 20 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Data.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index be1fe753..f61478c8 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -83,8 +83,11 @@ object DataMirror {
     requireIsHardware(target, "node requested directionality on")
     target.direction
   }
-  // TODO: really not a reflection-style API, but a workaround for dir in the compatibility package
-  def isSynthesizable(target: Data) = target.hasBinding
+
+  // Internal reflection-style APIs, subject to change and removal whenever.
+  object internal {
+    def isSynthesizable(target: Data) = target.hasBinding
+  }
 }
 
 /** Creates a clone of the super-type of the input elements. Super-type is defined as:
@@ -379,9 +382,27 @@ abstract class Data extends HasId {
   def toPrintable: Printable
 }
 
-object Wire {
-  // No source info since Scala macros don't yet support named / default arguments.
-  def apply[T <: Data](dummy: Int = 0, init: T)(implicit compileOptions: CompileOptions): T = {
+trait WireFactory {
+  def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
+    if (compileOptions.declaredTypeMustBeUnbound) {
+      requireIsChiselType(t, "wire type")
+    }
+    val x = t.chiselCloneType
+
+    // Bind each element of x to being a Wire
+    x.bind(WireBinding(Builder.forcedUserModule))
+
+    pushCommand(DefWire(sourceInfo, x))
+    pushCommand(DefInvalid(sourceInfo, x.ref))
+
+    x
+  }
+}
+
+object Wire extends WireFactory
+
+object WireInit {
+  def apply[T <: Data](init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     val model = (init.litArg match {
       // For e.g. Wire(init=0.U(k.W)), fix the Reg's width to k
       case Some(lit) if lit.forcedWidth => init.chiselCloneType
@@ -393,24 +414,11 @@ object Wire {
     apply(model, init)
   }
 
-  // No source info since Scala macros don't yet support named / default arguments.
-  def apply[T <: Data](t: T, init: T)(implicit compileOptions: CompileOptions): T = {
+  def apply[T <: Data](t: T, init: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
     implicit val noSourceInfo = UnlocatableSourceInfo
-    val x = apply(t)
+    val x = Wire(t)
     requireIsHardware(init, "wire initializer")
     x := init
     x
   }
-
-  def apply[T <: Data](t: T)(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): T = {
-    val x = t.chiselCloneType
-
-    // Bind each element of x to being a Wire
-    x.bind(WireBinding(Builder.forcedUserModule))
-
-    pushCommand(DefWire(sourceInfo, x))
-    pushCommand(DefInvalid(sourceInfo, x.ref))
-
-    x
-  }
 }
-- 
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