From 7834f0ada9f8bcfc28c1d6124f63acdcaa2d4755 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 9 May 2018 17:07:13 -0700
Subject: work on new style literal accessors

---
 chiselFrontend/src/main/scala/chisel3/core/Clock.scala | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Clock.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
index f682310b..55f76160 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Clock.scala
@@ -23,6 +23,8 @@ sealed class Clock extends Element(Width(1)) {
     case _ => super.badConnect(that)(sourceInfo)
   }
 
+  override def litToBigIntOption = None
+
   /** Not really supported */
   def toPrintable: Printable = PString("CLOCK")
 
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