From e07248b8f6022fafdb84f5d1c0ebe3fc90a5475a Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Thu, 13 Apr 2017 22:59:00 -0700
Subject: Module Hierarchy Refactor (#469)

---
 chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
index 73573bb1..015629e5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/ChiselAnnotation.scala
@@ -18,7 +18,7 @@ case class ChiselAnnotation(component: InstanceId, transformClass: Class[_ <: Tr
   def toFirrtl: Annotation = {
     val circuitName = CircuitName(component.pathName.split("""\.""").head)
     component match {
-      case m: Module =>
+      case m: BaseModule =>
         Annotation(
           ModuleName(m.name, circuitName), transformClass, value)
       case _ =>
-- 
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