From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 .../src/main/scala/chisel3/core/BlackBox.scala     | 55 ++++++++++++++++++++++
 1 file changed, 55 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
new file mode 100644
index 00000000..b634f021
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -0,0 +1,55 @@
+// See LICENSE for license details.
+
+package Chisel
+
+import internal.Builder.pushCommand
+import internal.firrtl.{ModuleIO, DefInvalid}
+import internal.sourceinfo.SourceInfo
+
+/** Defines a black box, which is a module that can be referenced from within
+  * Chisel, but is not defined in the emitted Verilog. Useful for connecting
+  * to RTL modules defined outside Chisel.
+  *
+  * @example
+  * {{{
+  * ... to be written once a spec is finalized ...
+  * }}}
+  */
+// REVIEW TODO: make Verilog parameters part of the constructor interface?
+abstract class BlackBox extends Module {
+  // Don't bother taking override_clock|reset, clock/reset locked out anyway
+  // TODO: actually implement this.
+  def setVerilogParameters(s: String): Unit = {}
+
+  // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
+  // Bypass standard clock, reset, io port declaration by flattening io
+  // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
+  override private[Chisel] def ports = io.elements.toSeq
+
+  // Do not do reflective naming of internal signals, just name io
+  override private[Chisel] def setRefs(): this.type = {
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+    // setRef is not called on the actual io.
+    // There is a risk of user improperly attempting to connect directly with io
+    // Long term solution will be to define BlackBox IO differently as part of
+    //   it not descending from the (current) Module
+    this
+  }
+
+  // Don't setup clock, reset
+  // Cann't invalide io in one bunch, must invalidate each part separately
+  override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+    case Some(p) => {
+      // Just init instance inputs
+      for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
+      this
+    }
+    case None => this
+  }
+
+  // Using null is horrible but these signals SHOULD NEVER be used:
+  override val clock = null
+  override val reset = null
+}
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 .../src/main/scala/chisel3/core/BlackBox.scala     | 28 ++++++++++++++--------
 1 file changed, 18 insertions(+), 10 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index b634f021..f2d9558d 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -1,10 +1,10 @@
 // See LICENSE for license details.
 
-package Chisel
+package chisel3.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.{ModuleIO, DefInvalid}
-import internal.sourceinfo.SourceInfo
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.sourceinfo.SourceInfo
 
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
@@ -24,23 +24,31 @@ abstract class BlackBox extends Module {
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
   // TODO(twigg): ? Really, overrides are bad, should extend BaseModule....
-  override private[Chisel] def ports = io.elements.toSeq
+  override private[core] def ports = io.elements.toSeq
 
   // Do not do reflective naming of internal signals, just name io
-  override private[Chisel] def setRefs(): this.type = {
-    for ((name, port) <- ports) {
-      port.setRef(ModuleIO(this, _namespace.name(name)))
-    }
+  override private[core] def setRefs(): this.type = {
     // setRef is not called on the actual io.
     // There is a risk of user improperly attempting to connect directly with io
     // Long term solution will be to define BlackBox IO differently as part of
     //   it not descending from the (current) Module
+    for ((name, port) <- ports) {
+      port.setRef(ModuleIO(this, _namespace.name(name)))
+    }
+    // We need to call forceName and onModuleClose on all of the sub-elements
+    // of the io bundle, but NOT on the io bundle itself.
+    // Doing so would cause the wrong names to be assigned, since their parent
+    // is now the module itself instead of the io bundle.
+    for (id <- _ids; if id ne io) {
+      id.forceName(default="T", _namespace)
+      id._onModuleClose
+    }
     this
   }
 
   // Don't setup clock, reset
   // Cann't invalide io in one bunch, must invalidate each part separately
-  override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
+  override private[core] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match {
     case Some(p) => {
       // Just init instance inputs
       for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref))
-- 
cgit v1.2.3