From ab951049c2c60402e2318ba863520d4a16c8288d Mon Sep 17 00:00:00 2001
From: Albert Chen
Date: Mon, 26 Nov 2018 09:47:28 -0800
Subject: Trim Stack Trace (#931)

- Trim stack trace to show better, reduced information to the user
- Add --full-stacktrace to FIRRTL option to show full stack trace---
 chiselFrontend/src/main/scala/chisel3/core/Binding.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/Binding.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index b3b754de..60235477 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -1,10 +1,11 @@
 package chisel3.core
 
+import chisel3.internal.ChiselException
 import chisel3.internal.Builder.{forcedModule}
 import chisel3.internal.firrtl.LitArg
 
 object Binding {
-  class BindingException(message: String) extends Exception(message)
+  class BindingException(message: String) extends ChiselException(message)
   /** A function expected a Chisel type but got a hardware object
     */
   case class ExpectedChiselTypeException(message: String) extends BindingException(message)
-- 
cgit v1.2.3