From c5f9ea3133ef363ff8944e17d94fea79767b6bed Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 10:01:23 -0700
Subject: Rename "Chisel" to "chisel3" (only git mv).

---
 .../src/main/scala/chisel3/core/BiConnect.scala    | 190 +++++++++++++++++++++
 1 file changed, 190 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
new file mode 100644
index 00000000..42d85bfb
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -0,0 +1,190 @@
+package Chisel
+
+import internal.Builder.pushCommand
+import internal.firrtl.Connect
+import scala.language.experimental.macros
+import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+
+/**
+* BiConnect.connect executes a bidirectional connection element-wise.
+*
+* Note that the arguments are left and right (not source and sink) so the
+* intent is for the operation to be commutative.
+*
+* The connect operation will recurse down the left Data (with the right Data).
+* An exception will be thrown if a movement through the left cannot be matched
+* in the right (or if the right side has extra fields).
+*
+* See elemConnect for details on how the root connections are issued.
+*
+*/
+
+object BiConnect {
+  // These are all the possible exceptions that can be thrown.
+  case class BiConnectException(message: String) extends Exception(message)
+  // These are from element-level connection
+  def BothDriversException =
+    BiConnectException(": Both Left and Right are drivers")
+  def NeitherDriverException =
+    BiConnectException(": Neither Left nor Right is a driver")
+  def UnknownDriverException =
+    BiConnectException(": Locally unclear whether Left or Right (both internal)")
+  def UnknownRelationException =
+    BiConnectException(": Left or Right unavailable to current module.")
+  // These are when recursing down aggregate types
+  def MismatchedVecException =
+    BiConnectException(": Left and Right are different length Vecs.")
+  def MissingLeftFieldException(field: String) =
+    BiConnectException(s".$field: Left Bundle missing field ($field).")
+  def MissingRightFieldException(field: String) =
+    BiConnectException(s": Right Bundle missing field ($field).")
+  def MismatchedException(left: String, right: String) =
+    BiConnectException(s": Left ($left) and Right ($right) have different types.")
+
+  /** This function is what recursively tries to connect a left and right together
+  *
+  * There is some cleverness in the use of internal try-catch to catch exceptions
+  * during the recursive decent and then rethrow them with extra information added.
+  * This gives the user a 'path' to where in the connections things went wrong.
+  */
+  def connect(sourceInfo: SourceInfo, left: Data, right: Data, context_mod: Module): Unit =
+    (left, right) match {
+      // Handle element case (root case)
+      case (left_e: Element, right_e: Element) => {
+        elemConnect(sourceInfo, left_e, right_e, context_mod)
+        // TODO(twigg): Verify the element-level classes are connectable
+      }
+      // Handle Vec case
+      case (left_v: Vec[Data @unchecked], right_v: Vec[Data @unchecked]) => {
+        if(left_v.length != right_v.length) { throw MismatchedVecException }
+        for(idx <- 0 until left_v.length) {
+          try {
+            connect(sourceInfo, left_v(idx), right_v(idx), context_mod)
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
+          }
+        }
+      }
+      // Handle Bundle case
+      case (left_b: Bundle, right_b: Bundle) => {
+        // Verify right has no extra fields that left doesn't have
+        for((field, right_sub) <- right_b.elements) {
+          if(!left_b.elements.isDefinedAt(field)) throw MissingLeftFieldException(field)
+        }
+        // For each field in left, descend with right
+        for((field, left_sub) <- left_b.elements) {
+          try {
+            right_b.elements.get(field) match {
+              case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
+              case None => throw MissingRightFieldException(field)
+            }
+          } catch {
+            case BiConnectException(message) => throw BiConnectException(s".$field$message")
+          }
+        }
+      }
+      // Left and right are different subtypes of Data so fail
+      case (left, right) => throw MismatchedException(left.toString, right.toString)
+    }
+
+  // These functions (finally) issue the connection operation
+  // Issue with right as sink, left as source
+  private def issueConnectL2R(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, right.lref, left.ref))
+  }
+  // Issue with left as sink, right as source
+  private def issueConnectR2L(left: Element, right: Element)(implicit sourceInfo: SourceInfo): Unit = {
+    pushCommand(Connect(sourceInfo, left.lref, right.ref))
+  }
+
+  // This function checks if element-level connection operation allowed.
+  // Then it either issues it or throws the appropriate exception.
+  def elemConnect(implicit sourceInfo: SourceInfo, left: Element, right: Element, context_mod: Module): Unit = {
+    import Direction.{Input, Output} // Using extensively so import these
+    // If left or right have no location, assume in context module
+    // This can occur if one of them is a literal, unbound will error previously
+    val left_mod: Module  = left.binding.location.getOrElse(context_mod)
+    val right_mod: Module = right.binding.location.getOrElse(context_mod)
+
+    val left_direction: Option[Direction] = left.binding.direction
+    val right_direction: Option[Direction] = right.binding.direction
+    // None means internal
+
+    // CASE: Context is same module as left node and right node is in a child module
+    if( (left_mod == context_mod) &&
+        (right_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, right node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CHILD MOD
+        case (Some(Input),  Some(Input))  => issueConnectL2R(left, right)
+        case (None,         Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectR2L(left, right)
+        case (None,         Some(Output)) => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Output)) => throw BothDriversException
+        case (Some(Output), Some(Input))  => throw NeitherDriverException
+        case (_,            None)         => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module as right node and left node is in child module
+    else if( (right_mod == context_mod) &&
+             (left_mod._parent.map(_ == context_mod).getOrElse(false)) ) {
+      // Thus, left node better be a port node and thus have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CURRENT MOD
+        case (Some(Input),  Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Input),  None)         => issueConnectR2L(left, right)
+
+        case (Some(Output), Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Output), None)         => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Output)) => throw NeitherDriverException
+        case (Some(Output), Some(Input))  => throw BothDriversException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // CASE: Context is same module that both left node and right node are in
+    else if( (context_mod == left_mod) && (context_mod == right_mod) ) {
+      (left_direction, right_direction) match {
+        //    CURRENT MOD   CURRENT MOD
+        case (Some(Input),  Some(Output)) => issueConnectL2R(left, right)
+        case (Some(Input),  None)         => issueConnectL2R(left, right)
+        case (None,         Some(Output)) => issueConnectL2R(left, right)
+
+        case (Some(Output), Some(Input))  => issueConnectR2L(left, right)
+        case (Some(Output), None)         => issueConnectR2L(left, right)
+        case (None,         Some(Input))  => issueConnectR2L(left, right)
+
+        case (Some(Input),  Some(Input))  => throw BothDriversException
+        case (Some(Output), Some(Output)) => throw NeitherDriverException
+        case (None,         None)         => throw UnknownDriverException
+      }
+    }
+
+    // CASE: Context is the parent module of both the module containing left node
+    //                                        and the module containing right node
+    //   Note: This includes case when left and right in same module but in parent
+    else if( (left_mod._parent.map(_ == context_mod).getOrElse(false)) &&
+             (right_mod._parent.map(_ == context_mod).getOrElse(false))
+    ) {
+      // Thus both nodes must be ports and have a direction hint
+      (left_direction, right_direction) match {
+        //    CHILD MOD     CHILD MOD
+        case (Some(Input),  Some(Output)) => issueConnectR2L(left, right)
+        case (Some(Output), Some(Input))  => issueConnectL2R(left, right)
+
+        case (Some(Input),  Some(Input))  => throw NeitherDriverException
+        case (Some(Output), Some(Output)) => throw BothDriversException
+        case (_, None)                    => throw UnknownRelationException
+        case (None, _)                    => throw UnknownRelationException
+      }
+    }
+
+    // Not quite sure where left and right are compared to current module
+    // so just error out
+    else throw UnknownRelationException
+  }
+}
-- 
cgit v1.2.3


From 12810b5efe6a8f872fbc1c63cdfb835ca354624f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 6 Jul 2016 09:31:47 -0700
Subject: Update Chisel -> chisel3 references.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 42d85bfb..cb76159a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -1,9 +1,9 @@
-package Chisel
+package chisel3.core
 
-import internal.Builder.pushCommand
-import internal.firrtl.Connect
+import chisel3.internal.Builder.pushCommand
+import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
-import internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
-- 
cgit v1.2.3


From 4ab2aa0e9209000fb0ba1299ac18db2e033f708f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 12 Aug 2016 14:17:52 -0700
Subject: Use compileOptions to determine if Missing...FieldExceptions are
 thrown.

---
 .../src/main/scala/chisel3/core/BiConnect.scala          | 16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index cb76159a..71de50f6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -1,9 +1,9 @@
 package chisel3.core
 
-import chisel3.internal.Builder.pushCommand
+import chisel3.internal.Builder.{compileOptions, pushCommand}
 import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
-import chisel3.internal.sourceinfo.{SourceInfo, DeprecatedSourceInfo, UnlocatableSourceInfo, WireTransform, SourceInfoTransform}
+import chisel3.internal.sourceinfo._
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
@@ -69,14 +69,22 @@ object BiConnect {
       case (left_b: Bundle, right_b: Bundle) => {
         // Verify right has no extra fields that left doesn't have
         for((field, right_sub) <- right_b.elements) {
-          if(!left_b.elements.isDefinedAt(field)) throw MissingLeftFieldException(field)
+          if(!left_b.elements.isDefinedAt(field)) {
+            if (compileOptions.connectFieldsMustMatch) {
+              throw MissingLeftFieldException(field)
+            }
+          }
         }
         // For each field in left, descend with right
         for((field, left_sub) <- left_b.elements) {
           try {
             right_b.elements.get(field) match {
               case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
-              case None => throw MissingRightFieldException(field)
+              case None => {
+                if (compileOptions.connectFieldsMustMatch) {
+                  throw MissingRightFieldException(field)
+                }
+              }
             }
           } catch {
             case BiConnectException(message) => throw BiConnectException(s".$field$message")
-- 
cgit v1.2.3


From f41f2533c55e506f7d5bf2ee0198de4d9a3dbea3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Tue, 16 Aug 2016 11:59:20 -0700
Subject: Reduce rocket-chip elaboration errors.

---
 .../src/main/scala/chisel3/core/BiConnect.scala    | 24 ++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 71de50f6..b7fd65a5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -166,8 +166,28 @@ object BiConnect {
         case (Some(Output), None)         => issueConnectR2L(left, right)
         case (None,         Some(Input))  => issueConnectR2L(left, right)
 
-        case (Some(Input),  Some(Input))  => throw BothDriversException
-        case (Some(Output), Some(Output)) => throw NeitherDriverException
+        case (Some(Input),  Some(Input))  => {
+          if (compileOptions.portDeterminesDirection)
+          (left.binding, right.binding) match {
+            case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+            case (PortBinding(_, _), _) => issueConnectL2R(left, right)
+            case (_, PortBinding(_, _)) => issueConnectR2L(left, right)
+            case _ => throw BothDriversException
+          } else {
+            throw BothDriversException
+          }
+        }
+        case (Some(Output), Some(Output)) => {
+          if (compileOptions.portDeterminesDirection)
+            (left.binding, right.binding) match {
+              case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+              case (PortBinding(_, _), _) => issueConnectR2L(left, right)
+              case (_, PortBinding(_, _)) => issueConnectL2R(left, right)
+              case _ => throw BothDriversException
+            } else {
+            throw BothDriversException
+          }
+        }
         case (None,         None)         => throw UnknownDriverException
       }
     }
-- 
cgit v1.2.3


From 7922f8d4998dd902ee18a6e85e4a404a1f29eb3f Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 17 Aug 2016 13:30:05 -0700
Subject: Rocket-chip updates. Assume LHSItOutput if neither side is driving.
 Restore Wire()'s removal of direction in binding.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index b7fd65a5..c40b85ad 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -188,7 +188,13 @@ object BiConnect {
             throw BothDriversException
           }
         }
-        case (None,         None)         => throw UnknownDriverException
+        case (None,         None)         => {
+          if (compileOptions.assumeLHSIsOutput) {
+            issueConnectR2L(left, right)
+          } else {
+            throw UnknownDriverException
+          }
+        }
       }
     }
 
-- 
cgit v1.2.3


From 5fcdd12fe92bd22f9cdfb8f5e39e510684b709bf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 09:33:51 -0700
Subject: Rename individual compile options. Stricter values are "true".
 Current default (not strict) values are "false".

---
 .../src/main/scala/chisel3/core/BiConnect.scala    | 28 ++++++++++++----------
 1 file changed, 15 insertions(+), 13 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index c40b85ad..857b25aa 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -167,32 +167,34 @@ object BiConnect {
         case (None,         Some(Input))  => issueConnectR2L(left, right)
 
         case (Some(Input),  Some(Input))  => {
-          if (compileOptions.portDeterminesDirection)
-          (left.binding, right.binding) match {
-            case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
-            case (PortBinding(_, _), _) => issueConnectL2R(left, right)
-            case (_, PortBinding(_, _)) => issueConnectR2L(left, right)
-            case _ => throw BothDriversException
-          } else {
+          if (compileOptions.dontAssumeDirectionality) {
             throw BothDriversException
+          } else {
+            (left.binding, right.binding) match {
+              case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
+              case (PortBinding(_, _), _) => issueConnectL2R(left, right)
+              case (_, PortBinding(_, _)) => issueConnectR2L(left, right)
+              case _ => throw BothDriversException
+            }
           }
         }
         case (Some(Output), Some(Output)) => {
-          if (compileOptions.portDeterminesDirection)
+          if (compileOptions.dontAssumeDirectionality) {
+            throw BothDriversException
+          } else {
             (left.binding, right.binding) match {
               case (PortBinding(_, _), PortBinding(_, _)) => throw BothDriversException
               case (PortBinding(_, _), _) => issueConnectR2L(left, right)
               case (_, PortBinding(_, _)) => issueConnectL2R(left, right)
               case _ => throw BothDriversException
-            } else {
-            throw BothDriversException
+            }
           }
         }
         case (None,         None)         => {
-          if (compileOptions.assumeLHSIsOutput) {
-            issueConnectR2L(left, right)
-          } else {
+          if (compileOptions.dontAssumeDirectionality) {
             throw UnknownDriverException
+          } else {
+            issueConnectR2L(left, right)
           }
         }
       }
-- 
cgit v1.2.3


From 1973e4d7333e2c57be4bcb7204210ecafdacab93 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 29 Aug 2016 17:04:51 -0700
Subject: Check module-specific compile options. Import
 chisel3.NotStrict.CompileOptions in Chisel package. Add CompileOptions tests.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 857b25aa..969e5654 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -1,3 +1,5 @@
+// See LICENSE for license details.
+
 package chisel3.core
 
 import chisel3.internal.Builder.{compileOptions, pushCommand}
@@ -70,7 +72,7 @@ object BiConnect {
         // Verify right has no extra fields that left doesn't have
         for((field, right_sub) <- right_b.elements) {
           if(!left_b.elements.isDefinedAt(field)) {
-            if (compileOptions.connectFieldsMustMatch) {
+            if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
               throw MissingLeftFieldException(field)
             }
           }
@@ -81,7 +83,7 @@ object BiConnect {
             right_b.elements.get(field) match {
               case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
               case None => {
-                if (compileOptions.connectFieldsMustMatch) {
+                if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
                   throw MissingRightFieldException(field)
                 }
               }
@@ -167,7 +169,7 @@ object BiConnect {
         case (None,         Some(Input))  => issueConnectR2L(left, right)
 
         case (Some(Input),  Some(Input))  => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -179,7 +181,7 @@ object BiConnect {
           }
         }
         case (Some(Output), Some(Output)) => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -191,7 +193,7 @@ object BiConnect {
           }
         }
         case (None,         None)         => {
-          if (compileOptions.dontAssumeDirectionality) {
+          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
             throw UnknownDriverException
           } else {
             issueConnectR2L(left, right)
-- 
cgit v1.2.3


From 4b88a5dd45337fa88178fe17324eef3661daf1b3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Sep 2016 10:21:57 -0700
Subject: Move connection implicits from Module constructor to connection
 methods. Eliminate builder compileOptions.

---
 .../src/main/scala/chisel3/core/BiConnect.scala    | 23 +++++++++++-----------
 1 file changed, 12 insertions(+), 11 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 969e5654..b0be1c38 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -2,10 +2,11 @@
 
 package chisel3.core
 
-import chisel3.internal.Builder.{compileOptions, pushCommand}
+import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
 import chisel3.internal.sourceinfo._
+import chisel3.internal.ExplicitCompileOptions
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
@@ -49,11 +50,11 @@ object BiConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  def connect(sourceInfo: SourceInfo, left: Data, right: Data, context_mod: Module): Unit =
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit =
     (left, right) match {
       // Handle element case (root case)
       case (left_e: Element, right_e: Element) => {
-        elemConnect(sourceInfo, left_e, right_e, context_mod)
+        elemConnect(sourceInfo, connectCompileOptions, left_e, right_e, context_mod)
         // TODO(twigg): Verify the element-level classes are connectable
       }
       // Handle Vec case
@@ -61,7 +62,7 @@ object BiConnect {
         if(left_v.length != right_v.length) { throw MismatchedVecException }
         for(idx <- 0 until left_v.length) {
           try {
-            connect(sourceInfo, left_v(idx), right_v(idx), context_mod)
+            connect(sourceInfo, connectCompileOptions, left_v(idx), right_v(idx), context_mod)
           } catch {
             case BiConnectException(message) => throw BiConnectException(s"($idx)$message")
           }
@@ -72,7 +73,7 @@ object BiConnect {
         // Verify right has no extra fields that left doesn't have
         for((field, right_sub) <- right_b.elements) {
           if(!left_b.elements.isDefinedAt(field)) {
-            if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
+            if (connectCompileOptions.connectFieldsMustMatch) {
               throw MissingLeftFieldException(field)
             }
           }
@@ -81,9 +82,9 @@ object BiConnect {
         for((field, left_sub) <- left_b.elements) {
           try {
             right_b.elements.get(field) match {
-              case Some(right_sub) => connect(sourceInfo, left_sub, right_sub, context_mod)
+              case Some(right_sub) => connect(sourceInfo, connectCompileOptions, left_sub, right_sub, context_mod)
               case None => {
-                if (compileOptions.connectFieldsMustMatch || context_mod.compileOptions.connectFieldsMustMatch) {
+                if (connectCompileOptions.connectFieldsMustMatch) {
                   throw MissingRightFieldException(field)
                 }
               }
@@ -109,7 +110,7 @@ object BiConnect {
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
-  def elemConnect(implicit sourceInfo: SourceInfo, left: Element, right: Element, context_mod: Module): Unit = {
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
     import Direction.{Input, Output} // Using extensively so import these
     // If left or right have no location, assume in context module
     // This can occur if one of them is a literal, unbound will error previously
@@ -169,7 +170,7 @@ object BiConnect {
         case (None,         Some(Input))  => issueConnectR2L(left, right)
 
         case (Some(Input),  Some(Input))  => {
-          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
+          if (connectCompileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -181,7 +182,7 @@ object BiConnect {
           }
         }
         case (Some(Output), Some(Output)) => {
-          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
+          if (connectCompileOptions.dontAssumeDirectionality) {
             throw BothDriversException
           } else {
             (left.binding, right.binding) match {
@@ -193,7 +194,7 @@ object BiConnect {
           }
         }
         case (None,         None)         => {
-          if (compileOptions.dontAssumeDirectionality || context_mod.compileOptions.dontAssumeDirectionality) {
+          if (connectCompileOptions.dontAssumeDirectionality) {
             throw UnknownDriverException
           } else {
             issueConnectR2L(left, right)
-- 
cgit v1.2.3


From 53721ff4fd53f27edd75de8eb649a2e20390cceb Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 15 Sep 2016 15:43:52 -0700
Subject: add optional directionality assumption to BiConnect.elemConnect

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index b0be1c38..ce70a19a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -217,8 +217,18 @@ object BiConnect {
 
         case (Some(Input),  Some(Input))  => throw NeitherDriverException
         case (Some(Output), Some(Output)) => throw BothDriversException
-        case (_, None)                    => throw UnknownRelationException
-        case (None, _)                    => throw UnknownRelationException
+        case (_, None)                    =>
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw UnknownRelationException
+          } else {
+            issueConnectR2L(left, right)
+          }
+        case (None, _)                    =>
+          if (connectCompileOptions.dontAssumeDirectionality) {
+            throw UnknownRelationException
+          } else {
+            issueConnectR2L(left, right)
+          }
       }
     }
 
-- 
cgit v1.2.3


From eb5e5dc30019be342b7a0534b425bf33b7984ce3 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 11:44:09 -0700
Subject: Massive rename of CompileOptions. Massage CompileOption names in an
 attempt to preserve default (Strict) CompileOptions in the absence of
 explicit imports. NOTE: Since the default is now strict, we may encounter
 errors when we generate connections for clients (i.e., in Vec.do_apply() when
 we wire up a sequence). We should really thread the CompileOptions through
 the macro system so the client's implicits are used.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index ce70a19a..a6b9cda3 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -6,7 +6,7 @@ import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
 import chisel3.internal.sourceinfo._
-import chisel3.internal.ExplicitCompileOptions
+import chisel3.ImplicitCompileOptions
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
@@ -50,7 +50,7 @@ object BiConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  def connect(sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit =
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit =
     (left, right) match {
       // Handle element case (root case)
       case (left_e: Element, right_e: Element) => {
@@ -110,7 +110,7 @@ object BiConnect {
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
-  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ExplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
     import Direction.{Input, Output} // Using extensively so import these
     // If left or right have no location, assume in context module
     // This can occur if one of them is a literal, unbound will error previously
-- 
cgit v1.2.3


From 96fb6a5e2c781b20470d02eac186b1b129c20bdf Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 14:57:42 -0700
Subject: Consolidate CompileOptions and re-enable NotStrict pending macro
 work.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index a6b9cda3..16bde731 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -6,7 +6,7 @@ import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
 import chisel3.internal.sourceinfo._
-import chisel3.ImplicitCompileOptions
+//import chisel3.CompileOptions
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
@@ -50,7 +50,7 @@ object BiConnect {
   * during the recursive decent and then rethrow them with extra information added.
   * This gives the user a 'path' to where in the connections things went wrong.
   */
-  def connect(sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Data, right: Data, context_mod: Module): Unit =
+  def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: Module): Unit =
     (left, right) match {
       // Handle element case (root case)
       case (left_e: Element, right_e: Element) => {
@@ -110,7 +110,7 @@ object BiConnect {
 
   // This function checks if element-level connection operation allowed.
   // Then it either issues it or throws the appropriate exception.
-  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: ImplicitCompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
+  def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: Module): Unit = {
     import Direction.{Input, Output} // Using extensively so import these
     // If left or right have no location, assume in context module
     // This can occur if one of them is a literal, unbound will error previously
-- 
cgit v1.2.3


From 398edafd809c3abda751432c51a07b6b1158ecbd Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 29 Sep 2016 15:43:34 -0700
Subject: Manual dead code elimination.

---
 chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala | 1 -
 1 file changed, 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
index 16bde731..efecf343 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala
@@ -6,7 +6,6 @@ import chisel3.internal.Builder.pushCommand
 import chisel3.internal.firrtl.Connect
 import scala.language.experimental.macros
 import chisel3.internal.sourceinfo._
-//import chisel3.CompileOptions
 
 /**
 * BiConnect.connect executes a bidirectional connection element-wise.
-- 
cgit v1.2.3