From fbf5e6f1a0e8bf535d465b748ad554575fe62156 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Sun, 22 Mar 2020 18:13:58 -0700 Subject: Rename subprojects to more canonical names * Rename coreMacros to macros * Rename chiselFrontend to core Also make each subproject publish with "chisel3-" as a prefix --- .../src/main/scala/chisel3/aop/Aspect.scala | 40 ---------------------- 1 file changed, 40 deletions(-) delete mode 100644 chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala (limited to 'chiselFrontend/src/main/scala/chisel3/aop') diff --git a/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala b/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala deleted file mode 100644 index 9f10a0dd..00000000 --- a/chiselFrontend/src/main/scala/chisel3/aop/Aspect.scala +++ /dev/null @@ -1,40 +0,0 @@ -// See LICENSE for license details. - -package chisel3.aop - -import chisel3.RawModule -import firrtl.annotations.{Annotation, NoTargetAnnotation} -import firrtl.options.Unserializable -import firrtl.AnnotationSeq - -/** Represents an aspect of a Chisel module, by specifying - * what behavior should be done to instance, via the FIRRTL Annotation Mechanism - * @tparam T Type of top-level module - */ -abstract class Aspect[T <: RawModule] extends Annotation with Unserializable with NoTargetAnnotation { - /** Convert this Aspect to a seq of FIRRTL annotation - * @param top - * @return - */ - def toAnnotation(top: T): AnnotationSeq - - /** Called by [[chisel3.stage.phases.AspectPhase]] to resolve this Aspect into annotations - * @param top - * @return - */ - private[chisel3] def resolveAspect(top: RawModule): AnnotationSeq = { - toAnnotation(top.asInstanceOf[T]) - } -} - -/** Holds utility functions for Aspect stuff */ -object Aspect { - - /** Converts elaborated Chisel components to FIRRTL modules - * @param chiselIR - * @return - */ - def getFirrtl(chiselIR: chisel3.internal.firrtl.Circuit): firrtl.ir.Circuit = { - chisel3.internal.firrtl.Converter.convert(chiselIR) - } -} -- cgit v1.2.3