From 36ad324754dbcad3afceb80ad2e79051c7eb9a9e Mon Sep 17 00:00:00 2001
From: Kamyar Mohajerani
Date: Wed, 28 Aug 2019 13:22:50 -0400
Subject: refactor out _Factory traits + address EOF WS

---
 .../src/main/scala/chisel3/SIntFactory.scala       | 30 ++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/SIntFactory.scala

(limited to 'chiselFrontend/src/main/scala/chisel3/SIntFactory.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala b/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala
new file mode 100644
index 00000000..607e2e35
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/SIntFactory.scala
@@ -0,0 +1,30 @@
+// See LICENSE for license details.
+
+package chisel3
+
+import chisel3.internal.firrtl.{KnownSIntRange, NumericBound, Range, SLit, Width}
+
+// scalastyle:off method.name
+
+trait SIntFactory {
+  /** Create an SInt type with inferred width. */
+  def apply(): SInt = apply(Width())
+  /** Create a SInt type or port with fixed width. */
+  def apply(width: Width): SInt = new SInt(width)
+
+  /** Create a SInt with the specified range */
+  def apply(range: Range): SInt = {
+    apply(range.getWidth)
+  }
+  /** Create a SInt with the specified range */
+  def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
+    apply(KnownSIntRange(range._1, range._2))
+  }
+
+   /** Create an SInt literal with specified width. */
+  protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
+    val lit = SLit(value, width)
+    val result = new SInt(lit.width)
+    lit.bindLitArg(result)
+  }
+}
-- 
cgit v1.2.3