From 92d88ffbe1663b4aa917c6c8b66a4fd697282410 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 5 Nov 2019 13:41:47 -0800
Subject: Support literals cast to aggregates as async reset reg init values
 (#1225)

Accomplished by changing the code gen for casting literals to
aggregates. Rather than connecting the literal to a wire that is then
bit selected from, just bit select from the literal which saves the
creation of an intermediate wire and matches FIRRTL's semantics for
legal async reset initial values.---
 chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'chiselFrontend/src/main/scala/chisel3/Aggregate.scala')

diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
index ba9afd5b..eaa56c36 100644
--- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala
@@ -65,7 +65,7 @@ sealed abstract class Aggregate extends Data {
   private[chisel3] override def connectFromBits(that: Bits)(implicit sourceInfo: SourceInfo,
       compileOptions: CompileOptions): Unit = {
     var i = 0
-    val bits = WireDefault(UInt(this.width), that)  // handles width padding
+    val bits = if (that.isLit) that else WireDefault(UInt(this.width), that) // handles width padding
     for (x <- flatten) {
       val fieldWidth = x.getWidth
       if (fieldWidth > 0) {
-- 
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