From 66301b9042530a5265c18c97a0dab9022a0efc50 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 1 Jun 2016 12:17:25 -0700
Subject: Move chisel/... to chisel/core/..., make chisel/compatibility
 package/folder, move more things into utils

---
 .../src/main/scala/chisel/core/Printf.scala        | 36 ++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 chiselFrontend/src/main/scala/chisel/core/Printf.scala

(limited to 'chiselFrontend/src/main/scala/chisel/core/Printf.scala')

diff --git a/chiselFrontend/src/main/scala/chisel/core/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
new file mode 100644
index 00000000..27b72815
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
@@ -0,0 +1,36 @@
+// See LICENSE for license details.
+
+package chisel
+
+import scala.language.experimental.macros
+
+import internal._
+import internal.Builder.pushCommand
+import internal.firrtl._
+import internal.sourceinfo.SourceInfo
+
+object printf { // scalastyle:ignore object.name
+  /** Prints a message in simulation.
+    *
+    * Does not fire when in reset (defined as the encapsulating Module's
+    * reset). If your definition of reset is not the encapsulating Module's
+    * reset, you will need to gate this externally.
+    *
+    * May be called outside of a Module (like defined in a function), so
+    * functions using printf make the standard Module assumptions (single clock
+    * and single reset).
+    *
+    * @param fmt printf format string
+    * @param data format string varargs containing data to print
+    */
+  def apply(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+    when (!(Builder.dynamicContext.currentModule.get.reset)) {
+      printfWithoutReset(fmt, data:_*)
+    }
+  }
+
+  private[chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+    val clock = Builder.dynamicContext.currentModule.get.clock
+    pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
+  }
+}
-- 
cgit v1.2.3


From 69c984607e87cb62c82c99056b2664f11b968267 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 1 Jun 2016 12:46:05 -0700
Subject: Package split chisel core

---
 chiselFrontend/src/main/scala/chisel/core/Printf.scala | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

(limited to 'chiselFrontend/src/main/scala/chisel/core/Printf.scala')

diff --git a/chiselFrontend/src/main/scala/chisel/core/Printf.scala b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
index 27b72815..a7970816 100644
--- a/chiselFrontend/src/main/scala/chisel/core/Printf.scala
+++ b/chiselFrontend/src/main/scala/chisel/core/Printf.scala
@@ -1,13 +1,13 @@
 // See LICENSE for license details.
 
-package chisel
+package chisel.core
 
 import scala.language.experimental.macros
 
-import internal._
-import internal.Builder.pushCommand
-import internal.firrtl._
-import internal.sourceinfo.SourceInfo
+import chisel.internal._
+import chisel.internal.Builder.pushCommand
+import chisel.internal.firrtl._
+import chisel.internal.sourceinfo.SourceInfo
 
 object printf { // scalastyle:ignore object.name
   /** Prints a message in simulation.
@@ -29,7 +29,7 @@ object printf { // scalastyle:ignore object.name
     }
   }
 
-  private[chisel] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
+  private[core] def printfWithoutReset(fmt: String, data: Bits*)(implicit sourceInfo: SourceInfo) {
     val clock = Builder.dynamicContext.currentModule.get.clock
     pushCommand(Printf(sourceInfo, Node(clock), fmt, data.map((d: Bits) => d.ref)))
   }
-- 
cgit v1.2.3