From f1b09622fd66271b2fc152bbb3b04f256cea2064 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 26 Sep 2019 13:42:14 -0400 Subject: More README.md fixes - Scaladoc for "latest" is 2.11, so use a 2.11-style link - Use full path for SETUP.md - Switch migration guide to point to website version over wiki Signed-off-by: Schuyler Eldridge --- README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'README.md') diff --git a/README.md b/README.md index 9318608d..00fd3822 100644 --- a/README.md +++ b/README.md @@ -8,7 +8,7 @@ [**Chisel**](https://www.chisel-lang.org) is a hardware design language that facilitates **advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs**. Chisel adds hardware construction primitives to the [Scala](https://www.scala-lang.org) programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. -This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/chisel3/util/index.html), raising the level of abstraction in design while retaining fine-grained control. +This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the [Chisel Standard Library](https://www.chisel-lang.org/api/latest/#chisel3.util.package), raising the level of abstraction in design while retaining fine-grained control. For more information on the benefits of Chisel see: ["What benefits does Chisel offer over classic Hardware Description Languages?"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages) @@ -76,7 +76,7 @@ The [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chi ### Build Your Own Chisel Projects -See [the setup instructions](SETUP.md) for how to set up your environment to run Chisel locally. +See [the setup instructions](https://github.com/freechipsproject/chisel3/blob/master/SETUP.md) for how to set up your environment to run Chisel locally. When you're ready to build your own circuits in Chisel, **we recommend starting from the [Chisel Template](https://github.com/freechipsproject/chisel-template) repository**, which provides a pre-configured project, example design, and testbench. Follow the [chisel-template readme](https://github.com/freechipsproject/chisel-template) to get started. @@ -107,7 +107,7 @@ These simulation-based verification tools are available for Chisel: - [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel - [**Website**](https://www.chisel-lang.org) -If you are migrating from Chisel2, see [the migration guide on the wiki](https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2). +If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/chisel3-vs-chisel2.html). ### Data Types Overview These are the base data types for defining circuit components: -- cgit v1.2.3