From 783bcb8b3436e342a04169eaf967db2dbc58abc7 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Fri, 15 Dec 2023 09:22:44 -0800
Subject: Add abstract module

---
 AbstractModule.scala | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 AbstractModule.scala

(limited to 'AbstractModule.scala')

diff --git a/AbstractModule.scala b/AbstractModule.scala
new file mode 100644
index 00000000..2c2574ad
--- /dev/null
+++ b/AbstractModule.scala
@@ -0,0 +1,21 @@
+package chiselTests
+
+import chisel3._
+import chisel3.stage.ChiselStage
+
+class AbstractModule[T <: Data](params: T) extends Module[T] {
+  val node = IO(params)
+}
+
+class AbstractModuleContainer extends Module {
+  val mod1 = Module(new AbstractModule[UInt](Input(UInt(0.W))))
+  val mod2 = Module(new AbstractModule[UInt](Output(UInt(0.W))))
+  mod2.node := mod1.node
+}
+
+object main {
+  def main(args: Array[String]): Unit = {
+    // println(getVerilogString(new Example))
+    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
+  }
+}
-- 
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