From 9ea198e779eb32fa1b43a771e3b70d2b38063280 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 25 Sep 2019 14:51:12 -0400 Subject: Use line instead of empty H1 in README.md Signed-off-by: Schuyler Eldridge --- README.md | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 8493f929..13e38610 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,6 @@ ![Chisel 3](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/chisel_logo.svg?sanitize=true) -# +--- [![Join the chat at https://gitter.im/freechipsproject/chisel3](https://badges.gitter.im/freechipsproject/chisel3.svg)](https://gitter.im/freechipsproject/chisel3?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge) [![CircleCI](https://circleci.com/gh/freechipsproject/chisel3/tree/master.svg?style=shield)](https://circleci.com/gh/freechipsproject/chisel3/tree/master) @@ -12,7 +12,7 @@ This generator methodology enables the creation of re-usable components and libr For more information on the benefits of Chisel see: ["What benefits does Chisel offer over classic Hardware Description Languages?"](https://stackoverflow.com/questions/53007782/what-benefits-does-chisel-offer-over-classic-hardware-description-languages) -Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/freechipsproject/firrtl), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations. +Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](https://github.com/freechipsproject/firrtl), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations. ## What does Chisel code look like? @@ -51,15 +51,15 @@ class FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module { for (i <- 1 until coeffs.length) { zs(i) := zs(i-1) } - + // Do the multiplies val products = VecInit.tabulate(coeffs.length)(i => zs(i) * coeffs(i)) - + // Sum up the products io.out := products.reduce(_ + _) } ``` - + and use and re-use them across designs: ```scala val movingAverage3Filter = FirFilter(8.W, Seq(1.U, 1.U, 1.U)) // same 3-point moving average filter as before @@ -72,7 +72,7 @@ val triangleFilter = FirFilter(8.W, Seq(1.U, 2.U, 3.U, 2.U, 1.U)) // 5-point FI ### Bootcamp Interactive Tutorial The [**online Chisel Bootcamp**](https://mybinder.org/v2/gh/freechipsproject/chisel-bootcamp/master) is the recommended way to get started with and learn Chisel. -**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala. +**No setup is required** (it runs in the browser), nor does it assume any prior knowledge of Scala. ### Build Your Own Chisel Projects @@ -88,7 +88,7 @@ resolvers ++= Seq( ) libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.2-SNAPSHOT" libraryDependencies += "edu.berkeley.cs" %% "chisel-testers2" % "0.1-SNAPSHOT" -``` +``` ### Design Verification -- cgit v1.2.3 From 8efe7c925c78f3393cb3cf658e7c5d8416aa731e Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 25 Sep 2019 15:18:18 -0400 Subject: Add graphviz type hierarchy with built svg/png Signed-off-by: Schuyler Eldridge --- doc/images/Makefile | 12 + doc/images/type_hierarchy.dot | 52 +++ doc/images/type_hierarchy.png | Bin 18555 -> 34477 bytes doc/images/type_hierarchy.svg | 1035 +++++++++++------------------------------ 4 files changed, 323 insertions(+), 776 deletions(-) create mode 100644 doc/images/Makefile create mode 100644 doc/images/type_hierarchy.dot diff --git a/doc/images/Makefile b/doc/images/Makefile new file mode 100644 index 00000000..20a41d1f --- /dev/null +++ b/doc/images/Makefile @@ -0,0 +1,12 @@ +.PHONY: all + +sources = \ + type_hierarchy.dot + +all: $(sources:%.dot=%.svg) $(sources:%.dot=%.png) + +%.svg: %.dot + dot -Tsvg $< -o $@ + +%.png: %.dot + dot -Tpng $< -o $@ diff --git a/doc/images/type_hierarchy.dot b/doc/images/type_hierarchy.dot new file mode 100644 index 00000000..d3bf6eb4 --- /dev/null +++ b/doc/images/type_hierarchy.dot @@ -0,0 +1,52 @@ +digraph TypeHierarchy { + graph [rankdir=BT bgcolor="transparent"] + { node [style=filled,shape=box] + { node [fillcolor="#f7fbff"] + Data + Element + Bits Num + Aggregate + VecLike + "Chisel Internal" + } + { node [fillcolor="#e5f5e0"] + Bool UInt SInt FixedPoint + Reset + AsyncReset + Record + Bundle + Vec + "Chisel Types" + } + { node [fillcolor="#fcbba1"] + "User Types" + Ellipsis [label="..."] + } + + subgraph cluster_data_hierarchy { + color=transparent + Element + Bits Num + Reset + Bool UInt SInt FixedPoint + color=transparent + Aggregate + VecLike + Record + Bundle + Vec + + {Aggregate Element} -> Data + {Bits Reset} -> Element + {FixedPoint SInt UInt} -> {Bits Num} + Bool -> {UInt Reset} + Ellipsis -> Bundle -> Record -> Aggregate + Vec -> {Aggregate VecLike} + AsyncReset -> {Element Reset} + } + subgraph cluster_legend { + label=Legend + "User Types" -> "Chisel Types" -> "Chisel Internal" + } + } +} diff --git a/doc/images/type_hierarchy.png b/doc/images/type_hierarchy.png index 4856ab6c..f3947975 100644 Binary files a/doc/images/type_hierarchy.png and b/doc/images/type_hierarchy.png differ diff --git a/doc/images/type_hierarchy.svg b/doc/images/type_hierarchy.svg index c74a0eeb..c120daba 100644 --- a/doc/images/type_hierarchy.svg +++ b/doc/images/type_hierarchy.svg @@ -1,778 +1,261 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - - - - - - - Aggregate - - Element - - Vec - - UInt - - SInt - - Bits - - Bool - Data - - - Bundle - - - - - - Record - + + + + + +TypeHierarchy + +cluster_data_hierarchy + + + +cluster_legend + +Legend + + + +Data + +Data + + + +Element + +Element + + + +Element->Data + + + + + +Bits + +Bits + + + +Bits->Element + + + + + +Num + +Num + + + +Aggregate + +Aggregate + + + +Aggregate->Data + + + + + +VecLike + +VecLike + + + +Chisel Internal + +Chisel Internal + + + +Bool + +Bool + + + +UInt + +UInt + + + +Bool->UInt + + + + + +Reset + +Reset + + + +Bool->Reset + + + + + +UInt->Bits + + + + + +UInt->Num + + + + + +SInt + +SInt + + + +SInt->Bits + + + + + +SInt->Num + + + + + +FixedPoint + +FixedPoint + + + +FixedPoint->Bits + + + + + +FixedPoint->Num + + + + + +Reset->Element + + + + + +AsyncReset + +AsyncReset + + + +AsyncReset->Element + + + + + +AsyncReset->Reset + + + + + +Record + +Record + + + +Record->Aggregate + + + + + +Bundle + +Bundle + + + +Bundle->Record + + + + + +Vec + +Vec + + + +Vec->Aggregate + + + + + +Vec->VecLike + + + + + +Chisel Types + +Chisel Types + + + +Chisel Types->Chisel Internal + + + + + +User Types + +User Types + + + +User Types->Chisel Types + + + + + +Ellipsis + +... + + + +Ellipsis->Bundle + + + + -- cgit v1.2.3 From 70b59235cfef3c0391ddee0e406bc806e11a1557 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 25 Sep 2019 15:22:11 -0400 Subject: Use full URL links for images Signed-off-by: Schuyler Eldridge --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 13e38610..fb91897f 100644 --- a/README.md +++ b/README.md @@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: - + While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: @@ -112,7 +112,7 @@ If you are migrating from Chisel2, see [the migration guide on the wiki](https:/ ### Data Types Overview These are the base data types for defining circuit wires (abstract types which may not be instantiated are greyed out): -![Image](doc/images/type_hierarchy.png?raw=true) +![Image](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/type_hierarchy.svg?sanitize=true) ## Developer Documentation This section describes how to get started developing Chisel itself, including how to test your version locally against other projects that pull in Chisel using [sbt's managed dependencies](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html). -- cgit v1.2.3 From e0238a23176e416836e6647b91390695e1b366c4 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 25 Sep 2019 15:27:18 -0400 Subject: Simplify data types README description Signed-off-by: Schuyler Eldridge --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index fb91897f..f4c70ae3 100644 --- a/README.md +++ b/README.md @@ -110,7 +110,7 @@ These simulation-based verification tools are available for Chisel: If you are migrating from Chisel2, see [the migration guide on the wiki](https://github.com/ucb-bar/chisel3/wiki/Chisel3-vs-Chisel2). ### Data Types Overview -These are the base data types for defining circuit wires (abstract types which may not be instantiated are greyed out): +These are the base data types for defining circuit components: ![Image](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/type_hierarchy.svg?sanitize=true) -- cgit v1.2.3