From f210909e11f95cbc033898b22d3498ac7a7a87bc Mon Sep 17 00:00:00 2001
From: Jiuyang Liu
Date: Tue, 29 Jun 2021 09:47:43 +0800
Subject: deprecate getPorts with modulePorts. (#1945)

* deprecate getPorts with modulePorts.

* add doc to fullModulePorts and update deprecation notes.

Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>---
 core/src/main/scala/chisel3/Data.scala      | 4 +++-
 core/src/main/scala/chisel3/RawModule.scala | 1 +
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index 0832161e..5513035b 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -156,7 +156,9 @@ package experimental {
     // with compiled artifacts (vs. elaboration-time reflection)?
     def modulePorts(target: BaseModule): Seq[(String, Data)] = target.getChiselPorts
 
-    // Returns all module ports with underscore-qualified names
+    /** Returns all module ports with underscore-qualified names
+      * return includes [[Module.clock]] and [[Module.reset]]
+      */
     def fullModulePorts(target: BaseModule): Seq[(String, Data)] = {
       def getPortNames(name: String, data: Data): Seq[(String, Data)] = Seq(name -> data) ++ (data match {
         case _: Element => Seq()
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 4a60ca47..fadb8dae 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -36,6 +36,7 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions)
   //
   // For debuggers/testers, TODO: refactor out into proper public API
   private var _firrtlPorts: Option[Seq[firrtl.Port]] = None
+  @deprecated("Use DataMirror.fullModulePorts instead. this API will be removed in Chisel 3.6", "Chisel 3.5")
   lazy val getPorts = _firrtlPorts.get
 
   val compileOptions = moduleCompileOptions
-- 
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