From f10c95aa4ea2e1a7484a9e1629b006322ee0e753 Mon Sep 17 00:00:00 2001
From: grebe
Date: Wed, 23 May 2018 11:31:26 -0700
Subject: Add test for zero-width Mems. (#821)

---
 src/test/scala/chiselTests/Mem.scala | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/src/test/scala/chiselTests/Mem.scala b/src/test/scala/chiselTests/Mem.scala
index 56110d0f..60835d49 100644
--- a/src/test/scala/chiselTests/Mem.scala
+++ b/src/test/scala/chiselTests/Mem.scala
@@ -33,6 +33,17 @@ class SyncReadMemTester extends BasicTester {
   }
 }
 
+class SyncReadMemWithZeroWidthTester extends BasicTester {
+  val (cnt, _) = Counter(true.B, 3)
+  val mem      = SyncReadMem(2, UInt(0.W))
+  val rdata    = mem.read(0.U, true.B)
+
+  switch (cnt) {
+    is (1.U) { assert(rdata === 0.U) }
+    is (2.U) { stop() }
+  }
+}
+
 class MemorySpec extends ChiselPropSpec {
   property("Mem of Vec should work") {
     assertTesterPasses { new MemVecTester }
@@ -41,4 +52,8 @@ class MemorySpec extends ChiselPropSpec {
   property("SyncReadMem should work") {
     assertTesterPasses { new SyncReadMemTester }
   }
+
+  property("SyncReadMem should work with zero width entry") {
+    assertTesterPasses { new SyncReadMemWithZeroWidthTester }
+  }
 }
-- 
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