From e85bfebb5d661de41f9ccac300fb48bf92840cfe Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 7 Dec 2021 13:18:29 -0800
Subject: [docs] Remove body from minimizing output bits recipe (#2290)

Remove the body from the emitted Verilog. This was the original intent
of the example, and it avoids an issue where Jekyll was not able to
render the Markdown file due to Verilog concatenation looking like a
variable escape.---
 docs/src/cookbooks/cookbook.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md
index e23b158c..d4cf3030 100644
--- a/docs/src/cookbooks/cookbook.md
+++ b/docs/src/cookbooks/cookbook.md
@@ -431,6 +431,9 @@ Unlike `Vecs` which represent a singular Chisel type and must have the same widt
 
 ```scala mdoc:verilog
 chisel3.stage.ChiselStage.emitVerilog(new CountBits(4))
+  // remove the body of the module by removing everything after ');'
+  .split("\\);")
+  .head + ");\n"
 ```
 
 ## Predictable Naming
-- 
cgit v1.2.3