From e60761cf72ba572da0bb8387a4506f5c3e211ac9 Mon Sep 17 00:00:00 2001
From: Jack
Date: Fri, 11 Nov 2016 13:54:37 -0800
Subject: Add SourceInfo.makeMessage to better use SourceInfo in error messages

---
 .../src/main/scala/chisel3/internal/SourceInfo.scala     | 16 +++++++++++++---
 src/main/scala/chisel3/internal/firrtl/Emitter.scala     |  5 +----
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
index 5e3bf33e..f1130db4 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/SourceInfo.scala
@@ -19,9 +19,17 @@ import scala.reflect.macros.blackbox.Context
 
 /** Abstract base class for generalized source information.
   */
-sealed trait SourceInfo
+sealed trait SourceInfo {
+  /** A prettier toString
+    *
+    * Make a useful message if SourceInfo is available, nothing otherwise
+    */
+  def makeMessage(f: String => String): String
+}
 
-sealed trait NoSourceInfo extends SourceInfo
+sealed trait NoSourceInfo extends SourceInfo {
+  def makeMessage(f: String => String): String = ""
+}
 
 /** For when source info can't be generated because of a technical limitation, like for Reg because
   * Scala macros don't support named or default arguments.
@@ -34,7 +42,9 @@ case object DeprecatedSourceInfo extends NoSourceInfo
 
 /** For FIRRTL lines from a Scala source line.
   */
-case class SourceLine(filename: String, line: Int, col: Int) extends SourceInfo
+case class SourceLine(filename: String, line: Int, col: Int) extends SourceInfo {
+  def makeMessage(f: String => String): String = f(s"@[$filename $line:$col]")
+}
 
 /** Provides a macro that returns the source information at the invocation point.
   */
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 0793fd7d..3fb18893 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -39,10 +39,7 @@ private class Emitter(circuit: Circuit) {
         unindent()
         s"skip"
     }
-    e.sourceInfo match {
-      case SourceLine(filename, line, col) => s"${firrtlLine} @[${filename} ${line}:${col}]"
-      case _: NoSourceInfo => firrtlLine
-    }
+    firrtlLine + e.sourceInfo.makeMessage(" " + _)
   }
 
   // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
-- 
cgit v1.2.3


From 815b1c3cb311b7f4dfb7a2f00e0e2d62795bdc6b Mon Sep 17 00:00:00 2001
From: Jack
Date: Fri, 11 Nov 2016 14:37:03 -0800
Subject: Add checks for misuse or omission of Module()

Implemented by adding a Boolean to check for alternating invocations of object
Module.apply and the constructor of abstract class Module.
Fixes #192
---
 .../src/main/scala/chisel3/core/Module.scala       | 18 ++++++-
 .../src/main/scala/chisel3/internal/Builder.scala  |  7 +++
 src/test/scala/chiselTests/AnnotatingExample.scala |  4 +-
 src/test/scala/chiselTests/ChiselSpec.scala        |  2 +-
 src/test/scala/chiselTests/DeqIOSpec.scala         | 62 ----------------------
 src/test/scala/chiselTests/Module.scala            | 34 ++++++++++++
 6 files changed, 61 insertions(+), 66 deletions(-)
 delete mode 100644 src/test/scala/chiselTests/DeqIOSpec.scala

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index c3353d85..ca391091 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -25,9 +25,21 @@ object Module {
     // module de-duplication in FIRRTL emission.
     val childSourceInfo = UnlocatableSourceInfo
 
+    if (Builder.readyForModuleConstr) {
+      throwException("Error: Called Module() twice without instantiating a Module." +
+                     sourceInfo.makeMessage(" See " + _))
+    }
+    Builder.readyForModuleConstr = true
     val parent: Option[Module] = Builder.currentModule
-    val m = bc.setRefs() // This will set currentModule!
+
+    val m = bc.setRefs() // This will set currentModule and unset readyForModuleConstr!!!
     m._commands.prepend(DefInvalid(childSourceInfo, m.io.ref)) // init module outputs
+
+    if (Builder.readyForModuleConstr) {
+      throwException("Error: attempted to instantiate a Module, but nothing happened. " +
+                     "This is probably due to rewrapping a Module instance with Module()." +
+                     sourceInfo.makeMessage(" See " + _))
+    }
     Builder.currentModule = parent // Back to parent!
     val ports = m.computePorts
     val component = Component(m, m.name, ports, m._commands)
@@ -93,6 +105,10 @@ extends HasId {
   private[chisel3] val _commands = ArrayBuffer[Command]()
   private[core] val _ids = ArrayBuffer[HasId]()
   Builder.currentModule = Some(this)
+  if (!Builder.readyForModuleConstr) {
+    throwException("Error: attempted to instantiate a Module without wrapping it in Module().")
+  }
+  readyForModuleConstr = false
 
   /** Desired name of this module. */
   def desiredName = this.getClass.getName.split('.').last
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index b4b0e028..028ce628 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -146,6 +146,9 @@ private[chisel3] class DynamicContext() {
   val globalNamespace = new Namespace(None, Set())
   val components = ArrayBuffer[Component]()
   var currentModule: Option[Module] = None
+  // Set by object Module.apply before calling class Module constructor
+  // Used to distinguish between no Module() wrapping, multiple wrappings, and rewrapping
+  var readyForModuleConstr: Boolean = false
   val errors = new ErrorLog
 }
 
@@ -170,6 +173,10 @@ private[chisel3] object Builder {
       // A bare api call is, e.g. calling Wire() from the scala console).
     )
   }
+  def readyForModuleConstr: Boolean = dynamicContext.readyForModuleConstr
+  def readyForModuleConstr_=(target: Boolean): Unit = {
+    dynamicContext.readyForModuleConstr = target
+  }
 
   // TODO(twigg): Ideally, binding checks and new bindings would all occur here
   // However, rest of frontend can't support this yet.
diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index c84edf86..04228d6b 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -141,5 +141,5 @@ object MyDriver extends BackendCompilationUtilities {
   /**
     * illustrates a chisel3 style driver that, annotations can only processed within this structure
     */
-  def buildAnnotatedCircuit[T <: Module](gen: () => T): Map[String, String] = MyBuilder.build(Module(gen()))
-}
\ No newline at end of file
+  def buildAnnotatedCircuit[T <: Module](gen: () => T): Map[String, String] = MyBuilder.build(gen())
+}
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index d335bdf6..7b915c09 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -28,7 +28,7 @@ trait ChiselRunners extends Assertions {
 class ChiselFlatSpec extends FlatSpec with ChiselRunners with Matchers
 
 /** Spec base class for property-based testers. */
-class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks {
+class ChiselPropSpec extends PropSpec with ChiselRunners with PropertyChecks with Matchers {
 
   // Constrain the default number of instances generated for every use of forAll.
   implicit override val generatorDrivenConfig =
diff --git a/src/test/scala/chiselTests/DeqIOSpec.scala b/src/test/scala/chiselTests/DeqIOSpec.scala
deleted file mode 100644
index d41c50e5..00000000
--- a/src/test/scala/chiselTests/DeqIOSpec.scala
+++ /dev/null
@@ -1,62 +0,0 @@
-// See LICENSE for license details.
-
-package chiselTests
-
-import chisel3._
-import chisel3.testers.BasicTester
-import chisel3.util._
-
-/**
-  * Created by chick on 2/8/16.
-  */
-class UsesDeqIOInfo extends Bundle {
-  val test_width = 32
-
-  val info_data = UInt.width(test_width)
-}
-
-class UsesDeqIO extends Module {
-  val io = IO(new Bundle {
-    val in = chisel3.util.DeqIO(new UsesDeqIOInfo)
-    val out = chisel3.util.EnqIO(new UsesDeqIOInfo)
-  })
-}
-
-class DeqIOSpec extends ChiselFlatSpec {
-  runTester {
-    new BasicTester {
-      val dut = new UsesDeqIO
-/*
-      "DeqIO" should "set the direction of it's parameter to INPUT" in {
-        assert(dut.io.in.bits.info_data.dir === INPUT)
-      }
-      "DeqIO" should "create a valid input and ready output" in {
-        assert(dut.io.in.valid.dir === INPUT)
-        assert(dut.io.in.ready.dir === OUTPUT)
-      }
-      "EnqIO" should "set the  direction of it's parameter OUTPUT" in {
-        assert(dut.io.out.bits.info_data.dir === OUTPUT)
-      }
-      "EnqIO" should "create a valid input and ready output" in {
-        assert(dut.io.out.valid.dir === OUTPUT)
-        assert(dut.io.out.ready.dir === INPUT)
-      }
-
-      val in_clone = dut.io.in.cloneType
-      val out_clone = dut.io.out.cloneType
-
-      "A deqIO device" should "clone itself with it's directions intact" in {
-        assert(dut.io.in.bits.info_data.dir == in_clone.bits.info_data.dir)
-        assert(dut.io.in.ready.dir == in_clone.ready.dir)
-        assert(dut.io.in.valid.dir == in_clone.valid.dir)
-      }
-
-      "A enqIO device" should "clone itself with it's directions intact" in {
-        assert(dut.io.out.bits.info_data.dir == out_clone.bits.info_data.dir)
-        assert(dut.io.out.ready.dir == out_clone.ready.dir)
-        assert(dut.io.out.valid.dir == out_clone.valid.dir)
-      }
-      */
-    }
-  }
-}
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index 7a4050db..c902d073 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -69,6 +69,22 @@ class ModuleWhen extends Module {
   } otherwise { io.s.out := io.s.in }
 }
 
+class ModuleForgetWrapper extends Module {
+  val io = IO(new SimpleIO)
+  val inst = new PlusOne
+}
+
+class ModuleDoubleWrap extends Module {
+  val io = IO(new SimpleIO)
+  val inst = Module(Module(new PlusOne))
+}
+
+class ModuleRewrap extends Module {
+  val io = IO(new SimpleIO)
+  val inst = Module(new PlusOne)
+  val inst2 = Module(inst)
+}
+
 class ModuleSpec extends ChiselPropSpec {
 
   property("ModuleVec should elaborate") {
@@ -88,4 +104,22 @@ class ModuleSpec extends ChiselPropSpec {
   }
 
   ignore("ModuleWhenTester should return the correct result") { }
+
+  property("Forgetting a Module() wrapper should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleForgetWrapper }
+    }).getMessage should include("attempted to instantiate a Module without wrapping it")
+  }
+
+  property("Double wrapping a Module should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleDoubleWrap }
+    }).getMessage should include("Called Module() twice without instantiating a Module")
+  }
+
+  property("Rewrapping an already instantiated Module should result in an error") {
+    (the [ChiselException] thrownBy {
+      elaborate { new ModuleRewrap }
+    }).getMessage should include("This is probably due to rewrapping a Module instance")
+  }
 }
-- 
cgit v1.2.3


From 29f84617ea30c7dd30c9616bcdb9a1894b8a0762 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:23:25 -0800
Subject: Eliminate some doc warnings

---
 chiselFrontend/src/main/scala/chisel3/core/Binding.scala | 7 +++----
 src/main/scala/chisel3/Driver.scala                      | 2 +-
 src/main/scala/chisel3/util/Decoupled.scala              | 2 +-
 3 files changed, 5 insertions(+), 6 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
index 467cb4eb..3dfde7c2 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala
@@ -140,10 +140,9 @@ object Binding {
       }
     }
 
-    /** Diagnose a binding error caused by a missing IO() wrapper.
-      * @param element the element triggering the binding error.
-      * @return true if the element is a member of the module's io but ioDefined is false.
-      */
+    // Diagnose a binding error caused by a missing IO() wrapper.
+    // element is the element triggering the binding error.
+    // Returns true if the element is a member of the module's io but ioDefined is false.
     def isMissingIOWrapper(element: Element): Boolean = {
       element._parent match {
         case None => false
diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index a0713379..11a447d1 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -95,7 +95,7 @@ trait BackendCompilationUtilities {
   /** Generates a Verilator invocation to convert Verilog sources to C++
     * simulation sources.
     *
-    * The Verilator prefix will be V$dutFile, and running this will generate
+    * The Verilator prefix will be V\$dutFile, and running this will generate
     * C++ sources and headers as well as a makefile to compile them.
     *
     * @param dutFile name of the DUT .v without the .v extension
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index c9d57759..2f6effbd 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -230,7 +230,7 @@ extends Module(override_reset=override_reset) {
   * @param enq input (enqueue) interface to the queue, also determines width of queue elements
   * @param entries depth (number of elements) of the queue
   *
-  * @returns output (dequeue) interface from the queue
+  * @return output (dequeue) interface from the queue
   *
   * @example {{{
   * consumer.io.in <> Queue(producer.io.out, 16)
-- 
cgit v1.2.3


From b2afa964431c9f109cf10c83d5db49a8d5799b58 Mon Sep 17 00:00:00 2001
From: Stevo
Date: Fri, 18 Nov 2016 10:54:43 -0800
Subject: Shift register enable gates all stages, not just first

Also, remove no-longer-special case for n=1.---
 src/main/scala/chisel3/util/Reg.scala | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index 713a3b2e..f41d789c 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -55,10 +55,8 @@ object ShiftRegister
     */
   def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
     // The order of tests reflects the expected use cases.
-    if (n == 1) {
-      RegEnable(in, en)
-    } else if (n != 0) {
-      RegNext(apply(in, n-1, en))
+    if (n != 0) {
+      RegEnable(apply(in, n-1, en), en)
     } else {
       in
     }
-- 
cgit v1.2.3


From 6929ca0fc64b562f4852a49df617a1836e083563 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 27 Oct 2016 14:01:33 -0700
Subject: Change Verilator invocation to use O1

Workaround for:
http://www.veripool.org/issues/1101-Verilator-Fix-SmallName-for-ParamTypeDType
---
 src/main/scala/chisel3/Driver.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/main/scala/chisel3/Driver.scala b/src/main/scala/chisel3/Driver.scala
index 11a447d1..ab51ad25 100644
--- a/src/main/scala/chisel3/Driver.scala
+++ b/src/main/scala/chisel3/Driver.scala
@@ -119,13 +119,13 @@ trait BackendCompilationUtilities {
         "-Wno-WIDTH",
         "-Wno-STMTDLY",
         "--trace",
-        "-O0",
+        "-O1",
         "--top-module", topModule,
         "+define+TOP_TYPE=V" + dutFile,
         s"+define+PRINTF_COND=!$topModule.reset",
         s"+define+STOP_COND=!$topModule.reset",
         "-CFLAGS",
-        s"""-Wno-undefined-bool-conversion -O0 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
+        s"""-Wno-undefined-bool-conversion -O1 -DTOP_TYPE=V$dutFile -include V$dutFile.h""",
         "-Mdir", dir.toString,
         "--exe", cppHarness.toString)
     System.out.println(s"${command.mkString(" ")}") // scalastyle:ignore regex
-- 
cgit v1.2.3


From 822160cc8e76e70643fb56707bb39f6f7526b6fd Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Thu, 22 Sep 2016 22:38:33 -0700
Subject: Add support for parameterized BlackBoxes

Also restrict black boxes to not allow hardware inside of them since it was
being silently dropped anyway.

Resolves #289
---
 .../src/main/scala/chisel3/core/BlackBox.scala     | 18 +++++---
 .../src/main/scala/chisel3/core/Module.scala       | 10 ++++-
 .../src/main/scala/chisel3/internal/Builder.scala  |  5 ++-
 .../main/scala/chisel3/internal/firrtl/IR.scala    |  8 +++-
 .../scala/chisel3/internal/firrtl/Emitter.scala    | 24 ++++++++---
 src/main/scala/chisel3/package.scala               | 24 +++++++++++
 src/test/resources/BlackBoxTest.v                  | 25 +++++++++++
 src/test/scala/chiselTests/BlackBox.scala          | 49 ++++++++++++++++++----
 8 files changed, 140 insertions(+), 23 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
index 7fe429fa..85a57111 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/BlackBox.scala
@@ -3,11 +3,20 @@
 package chisel3.core
 
 import chisel3.internal.Builder.pushCommand
-import chisel3.internal.firrtl.{ModuleIO, DefInvalid}
+import chisel3.internal.firrtl._
+import chisel3.internal.throwException
 import chisel3.internal.sourceinfo.SourceInfo
 // TODO: remove this once we have CompileOptions threaded through the macro system.
 import chisel3.core.ExplicitCompileOptions.NotStrict
 
+/** Parameters for BlackBoxes */
+sealed abstract class Param
+case class IntParam(value: BigInt) extends Param
+case class DoubleParam(value: Double) extends Param
+case class StringParam(value: String) extends Param
+/** Unquoted String */
+case class RawParam(value: String) extends Param
+
 /** Defines a black box, which is a module that can be referenced from within
   * Chisel, but is not defined in the emitted Verilog. Useful for connecting
   * to RTL modules defined outside Chisel.
@@ -16,12 +25,9 @@ import chisel3.core.ExplicitCompileOptions.NotStrict
   * {{{
   * ... to be written once a spec is finalized ...
   * }}}
+  * @note The parameters API is experimental and may change
   */
-// REVIEW TODO: make Verilog parameters part of the constructor interface?
-abstract class BlackBox extends Module {
-  // Don't bother taking override_clock|reset, clock/reset locked out anyway
-  // TODO: actually implement this.
-  def setVerilogParameters(s: String): Unit = {}
+abstract class BlackBox(val params: Map[String, Param] = Map.empty[String, Param]) extends Module {
 
   // The body of a BlackBox is empty, the real logic happens in firrtl/Emitter.scala
   // Bypass standard clock, reset, io port declaration by flattening io
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index ca391091..62b6d5ce 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -41,8 +41,16 @@ object Module {
                      sourceInfo.makeMessage(" See " + _))
     }
     Builder.currentModule = parent // Back to parent!
+
     val ports = m.computePorts
-    val component = Component(m, m.name, ports, m._commands)
+    // Blackbox inherits from Module so we have to match on it first TODO fix
+    val component = m match {
+      case bb: BlackBox =>
+        DefBlackBox(bb, bb.name, ports, bb.params)
+      case mod: Module =>
+        mod._commands.prepend(DefInvalid(childSourceInfo, mod.io.ref)) // init module outputs
+        DefModule(mod, mod.name, ports, mod._commands)
+    }
     m._component = Some(component)
     Builder.components += component
     // Avoid referencing 'parent' in top module
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 028ce628..60ce6d5d 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -181,7 +181,10 @@ private[chisel3] object Builder {
   // TODO(twigg): Ideally, binding checks and new bindings would all occur here
   // However, rest of frontend can't support this yet.
   def pushCommand[T <: Command](c: T): T = {
-    forcedModule._commands += c
+    forcedModule match {
+      case _: BlackBox => throwException("Cannot add hardware to a BlackBox")
+      case m => m._commands += c
+    }
     c
   }
   def pushOp[T <: Data](cmd: DefPrim[T]): T = {
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 0f866c27..17b869f2 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -215,8 +215,14 @@ case class Connect(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class BulkConnect(sourceInfo: SourceInfo, loc1: Node, loc2: Node) extends Command
 case class ConnectInit(sourceInfo: SourceInfo, loc: Node, exp: Arg) extends Command
 case class Stop(sourceInfo: SourceInfo, clock: Arg, ret: Int) extends Command
-case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
 case class Port(id: Data, dir: Direction)
 case class Printf(sourceInfo: SourceInfo, clock: Arg, pable: Printable) extends Command
+abstract class Component extends Arg {
+  def id: Module
+  def name: String
+  def ports: Seq[Port]
+}
+case class DefModule(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component
+case class DefBlackBox(id: Module, name: String, ports: Seq[Port], params: Map[String, Param]) extends Component
 
 case class Circuit(name: String, components: Seq[Component])
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index 3fb18893..b8651828 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -2,6 +2,7 @@
 
 package chisel3.internal.firrtl
 import chisel3._
+import chisel3.experimental._
 import chisel3.internal.sourceinfo.{NoSourceInfo, SourceLine}
 
 private[chisel3] object Emitter {
@@ -42,6 +43,16 @@ private class Emitter(circuit: Circuit) {
     firrtlLine + e.sourceInfo.makeMessage(" " + _)
   }
 
+  private def emitParam(name: String, p: Param): String = {
+    val str = p match {
+      case IntParam(value) => value.toString
+      case DoubleParam(value) => value.toString
+      case StringParam(str) => "\"" + str + "\""
+      case RawParam(str) => "'" + str + "'"
+    }
+    s"parameter $name = $str"
+  }
+
   // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
   private val defnMap = collection.mutable.HashMap[(String, String), Component]()
 
@@ -61,12 +72,13 @@ private class Emitter(circuit: Circuit) {
         body ++= newline + emitPort(p)
       body ++= newline
 
-      m.id match {
-        case _: BlackBox =>
-          // TODO: BlackBoxes should be empty, but funkiness in Module() means
-          // it's not for now. Eventually, this should assert out.
-        case _: Module => for (cmd <- m.commands) {
-          body ++= newline + emit(cmd, m)
+      m match {
+        case bb: DefBlackBox =>
+          // Firrtl extmodule can overrule name
+          body ++= newline + s"defname = ${bb.id.desiredName}"
+          body ++= newline + (bb.params map { case (n, p) => emitParam(n, p) } mkString newline)
+        case mod: DefModule => for (cmd <- mod.commands) {
+          body ++= newline + emit(cmd, mod)
         }
       }
       body ++= newline
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index e0364868..3cdda971 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -179,4 +179,28 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   }
   def getModulePorts(m: Module): Seq[Port] = m.getPorts
   def getFirrtlDirection(d: Data): Direction = chisel3.core.Data.getFirrtlDirection(d)
+
+  /** Package for experimental features, which may have their API changed, be removed, etc.
+    *
+    * Because its contents won't necessarily have the same level of stability and support as
+    * non-experimental, you must explicitly import this package to use its contents.
+    */
+  object experimental {
+    type Param = chisel3.core.Param
+    type IntParam = chisel3.core.IntParam
+    val IntParam = chisel3.core.IntParam
+    type DoubleParam = chisel3.core.DoubleParam
+    val DoubleParam = chisel3.core.DoubleParam
+    type StringParam = chisel3.core.StringParam
+    val StringParam = chisel3.core.StringParam
+    type RawParam = chisel3.core.RawParam
+    val RawParam = chisel3.core.RawParam
+
+    // Implicit conversions for BlackBox Parameters
+    implicit def fromIntToIntParam(x: Int): IntParam = IntParam(BigInt(x))
+    implicit def fromLongToIntParam(x: Long): IntParam = IntParam(BigInt(x))
+    implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x)
+    implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x)
+    implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
+  }
 }
diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v
index 910b09ff..edf321a8 100644
--- a/src/test/resources/BlackBoxTest.v
+++ b/src/test/resources/BlackBoxTest.v
@@ -32,3 +32,28 @@ module BlackBoxConstant #(
 );
   assign out = VALUE;
 endmodule
+
+module BlackBoxStringParam #(
+  parameter string STRING = "zero"
+) (
+  output [31:0] out
+);
+  assign out = (STRING == "one" )? 1 :
+               (STRING == "two" )? 2 : 0;
+endmodule
+
+module BlackBoxRealParam #(
+  parameter real REAL = 0.0
+) (
+  output [63:0] out
+);
+  assign out = $realtobits(REAL);
+endmodule
+
+module BlackBoxTypeParam #(
+  parameter type T = bit
+) (
+  output T out
+);
+  assign out = 32'hdeadbeef;
+endmodule
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 344754e1..d8821134 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -6,6 +6,7 @@ import java.io.File
 import org.scalatest._
 
 import chisel3._
+import chisel3.experimental._
 import chisel3.testers.BasicTester
 import chisel3.util._
 //import chisel3.core.ExplicitCompileOptions.Strict
@@ -84,27 +85,55 @@ class BlackBoxWithClockTester extends BasicTester {
   when(end) { stop() }
 }
 
-/*
-// Must determine how to handle parameterized Verilog
-class BlackBoxConstant(value: Int) extends BlackBox {
-  val io = IO(new Bundle() {
-    val out = Output(UInt(width=log2Up(value)))
+class BlackBoxConstant(value: Int) extends BlackBox(
+    Map("VALUE" -> value, "WIDTH" -> log2Up(value + 1))) {
+  require(value >= 0, "value must be a UInt!")
+  val io = IO(new Bundle {
+    val out = UInt(width = log2Up(value + 1)).asOutput
+  })
+}
+
+class BlackBoxStringParam(str: String) extends BlackBox(Map("STRING" -> str)) {
+  val io = IO(new Bundle {
+    val out = UInt(width = 32)
+  })
+}
+
+class BlackBoxRealParam(dbl: Double) extends BlackBox(Map("REAL" -> dbl)) {
+  val io = IO(new Bundle {
+    val out = UInt(width = 64)
+  })
+}
+
+class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawParam(raw))) {
+  val io = IO(new Bundle {
+    val out = UInt(width = w)
   })
-  override val name = s"#(WIDTH=${log2Up(value)},VALUE=$value) "
 }
 
 class BlackBoxWithParamsTester extends BasicTester {
   val blackBoxOne  = Module(new BlackBoxConstant(1))
-  val blackBoxFour = Module(new BlackBoxConstant(4))
+  val blackBoxFour  = Module(new BlackBoxConstant(4))
+  val blackBoxStringParamOne = Module(new BlackBoxStringParam("one"))
+  val blackBoxStringParamTwo = Module(new BlackBoxStringParam("two"))
+  val blackBoxRealParamOne = Module(new BlackBoxRealParam(1.0))
+  val blackBoxRealParamNeg = Module(new BlackBoxRealParam(-1.0))
+  val blackBoxTypeParamBit = Module(new BlackBoxTypeParam(1, "bit"))
+  val blackBoxTypeParamWord = Module(new BlackBoxTypeParam(32, "bit [31:0]"))
 
   val (cycles, end) = Counter(Bool(true), 4)
 
   assert(blackBoxOne.io.out  === UInt(1))
   assert(blackBoxFour.io.out === UInt(4))
+  assert(blackBoxStringParamOne.io.out === UInt(1))
+  assert(blackBoxStringParamTwo.io.out === UInt(2))
+  assert(blackBoxRealParamOne.io.out === UInt(0x3ff0000000000000L))
+  assert(blackBoxRealParamNeg.io.out === UInt(BigInt("bff0000000000000", 16)))
+  assert(blackBoxTypeParamBit.io.out === UInt(1))
+  assert(blackBoxTypeParamWord.io.out === UInt("hdeadbeef", 32))
 
   when(end) { stop() }
 }
-*/
 
 class BlackBoxSpec extends ChiselFlatSpec {
   "A BlackBoxed inverter" should "work" in {
@@ -119,4 +148,8 @@ class BlackBoxSpec extends ChiselFlatSpec {
     assertTesterPasses({ new BlackBoxWithClockTester },
         Seq("/BlackBoxTest.v"))
   }
+  "BlackBoxes with parameters" should "work" in {
+    assertTesterPasses({ new BlackBoxWithParamsTester },
+        Seq("/BlackBoxTest.v"))
+  }
 }
-- 
cgit v1.2.3


From 667a26bddb6133e8b243061f8a5fc5fe586cc1ae Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 25 Oct 2016 13:46:44 -0700
Subject: Range macro initial impl

---
 .../scala/chisel3/internal/RangeTransform.scala    | 97 ++++++++++++++++++++++
 src/test/scala/chiselTests/RangeMacroTest.scala    | 31 +++++++
 2 files changed, 128 insertions(+)
 create mode 100644 coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
 create mode 100644 src/test/scala/chiselTests/RangeMacroTest.scala

diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
new file mode 100644
index 00000000..bbb36190
--- /dev/null
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -0,0 +1,97 @@
+// See LICENSE for license details.
+
+// Macro transforms that statically (at compile time) parse range specifiers and emit the raw
+// (non-human-friendly) range constructor calls.
+
+package chisel3.internal
+
+import scala.language.experimental.macros
+import scala.reflect.macros.blackbox.Context
+import scala.reflect.macros.whitebox
+
+class RangeTransform(val c: Context) {
+  import c.universe._
+  def apply(args: c.Tree*): c.Tree = {
+    val stringTrees = c.prefix.tree match {
+      case q"$_(scala.StringContext.apply(..$strings))" => strings
+      case _ => c.abort(c.enclosingPosition, s"Range macro unable to parse StringContext, got: ${showCode(c.prefix.tree)}")
+    }
+    val strings = stringTrees.map { tree => tree match {
+      case Literal(Constant(string: String)) => string
+      case _ => c.abort(c.enclosingPosition, s"Range macro unable to parse StringContext element, got: ${showRaw(tree)}")
+    } }
+
+    var nextStringIndex: Int = 1
+    var nextArgIndex: Int = 0
+    var currString: String = strings(0)
+
+    /** Mutably gets the next numeric value in the range specifier.
+      */
+    def getNextValue(): c.Tree = {
+      currString = currString.dropWhile(_ == ' ')  // allow whitespace
+      if (currString.isEmpty()) {
+        if (nextArgIndex >= args.length) {
+          c.abort(c.enclosingPosition, s"Incomplete range specifier, expected interpolated value")
+        }
+        val nextArg = args(nextArgIndex)
+        nextArgIndex += 1
+
+        if (nextStringIndex >= strings.length) {
+          c.abort(c.enclosingPosition, s"Incomplete range specifier")
+        }
+        currString = strings(nextStringIndex)
+        nextStringIndex += 1
+
+        nextArg
+      } else {
+        val nextStringVal = currString.takeWhile(!Set('[', '(', ' ', ',', ')', ']').contains(_))
+        currString = currString.substring(nextStringVal.length)
+        if (currString.isEmpty()) {
+          if (nextStringIndex >= strings.length) {
+            c.abort(c.enclosingPosition, s"Incomplete range specifier")
+          }
+          currString = strings(nextStringIndex)
+          nextStringIndex += 1
+        }
+        c.parse(nextStringVal)
+      }
+    }
+
+    // Currently, not allowed to have the end stops (inclusive / exclusive) be interpolated.
+    currString = currString.dropWhile(_ == ' ')
+    val startInclusive = currString(0) match {
+      case '[' => true
+      case '(' => false
+      case _ => c.abort(c.enclosingPosition, s"Unknown start inclusive/exclusive specifier, got: '${currString(0)}'")
+    }
+    currString = currString.substring(1)  // eat the inclusive/exclusive specifier
+    val minArg = getNextValue()
+    currString = currString.dropWhile(_ == ' ')
+    if (currString(0) != ',') {
+      c.abort(c.enclosingPosition, s"Incomplete range specifier, expected ','")
+    }
+    currString = currString.substring(1)  // eat the comma
+    val maxArg = getNextValue()
+    currString = currString.dropWhile(_ == ' ')
+    val endInclusive = currString(0) match {
+      case ']' => true
+      case ')' => false
+      case _ => c.abort(c.enclosingPosition, s"Unknown end inclusive/exclusive specifier, got: '${currString(0)}'")
+    }
+    currString = currString.substring(1)  // eat the inclusive/exclusive specifier
+    currString = currString.dropWhile(_ == ' ')
+
+    if (nextArgIndex < args.length) {
+      val unused = args.mkString("")
+      c.abort(c.enclosingPosition, s"Unused interpolated values in range specifier: '$unused'")
+    }
+    if (!currString.isEmpty || nextStringIndex < strings.length) {
+      val unused = currString + strings.slice(nextStringIndex, strings.length).mkString(", ")
+      c.abort(c.enclosingPosition, s"Unused characters in range specifier: '$unused'")
+    }
+
+    c.warning(c.enclosingPosition, s"$startInclusive ${showRaw(minArg)} ${showRaw(maxArg)} $endInclusive")
+
+    q""
+  }
+}
diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
new file mode 100644
index 00000000..797c75c4
--- /dev/null
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -0,0 +1,31 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import scala.language.experimental.macros
+import org.scalatest._
+import org.scalatest.prop._
+import chisel3.testers.BasicTester
+
+package object rangeMacroTest {
+
+implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+  def range(args: Any*): Unit = macro chisel3.internal.RangeTransform.apply
+}
+
+}
+
+import rangeMacroTest._
+
+/** Comprehensive test of static range parsing functionality.
+  * Note: negative (failure) conditions can't be tested because they will fail at compile time,
+  * before the testing environment is entered.
+  */
+@dump
+class RangeMacroTest extends ChiselPropSpec {
+  property("Range macros should work") {
+    def ducks() = {2}
+    range"  (0, ${ducks}]   "
+  }
+}
-- 
cgit v1.2.3


From 4245c8c31749d9031da4915708bb23ec82a56da2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 25 Oct 2016 16:59:20 -0700
Subject: Better testing, better parsing

---
 .../src/main/scala/chisel3/internal/RangeTransform.scala   | 14 ++++++--------
 src/test/scala/chiselTests/RangeMacroTest.scala            |  4 ++--
 2 files changed, 8 insertions(+), 10 deletions(-)

diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
index bbb36190..20142d5d 100644
--- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -31,7 +31,7 @@ class RangeTransform(val c: Context) {
       currString = currString.dropWhile(_ == ' ')  // allow whitespace
       if (currString.isEmpty()) {
         if (nextArgIndex >= args.length) {
-          c.abort(c.enclosingPosition, s"Incomplete range specifier, expected interpolated value")
+          c.abort(c.enclosingPosition, s"Incomplete range specifier")
         }
         val nextArg = args(nextArgIndex)
         nextArgIndex += 1
@@ -47,11 +47,7 @@ class RangeTransform(val c: Context) {
         val nextStringVal = currString.takeWhile(!Set('[', '(', ' ', ',', ')', ']').contains(_))
         currString = currString.substring(nextStringVal.length)
         if (currString.isEmpty()) {
-          if (nextStringIndex >= strings.length) {
-            c.abort(c.enclosingPosition, s"Incomplete range specifier")
-          }
-          currString = strings(nextStringIndex)
-          nextStringIndex += 1
+          c.abort(c.enclosingPosition, s"Incomplete range specifier")
         }
         c.parse(nextStringVal)
       }
@@ -62,7 +58,7 @@ class RangeTransform(val c: Context) {
     val startInclusive = currString(0) match {
       case '[' => true
       case '(' => false
-      case _ => c.abort(c.enclosingPosition, s"Unknown start inclusive/exclusive specifier, got: '${currString(0)}'")
+      case other => c.abort(c.enclosingPosition, s"Unknown start inclusive/exclusive specifier, got: '$other'")
     }
     currString = currString.substring(1)  // eat the inclusive/exclusive specifier
     val minArg = getNextValue()
@@ -76,7 +72,7 @@ class RangeTransform(val c: Context) {
     val endInclusive = currString(0) match {
       case ']' => true
       case ')' => false
-      case _ => c.abort(c.enclosingPosition, s"Unknown end inclusive/exclusive specifier, got: '${currString(0)}'")
+      case other => c.abort(c.enclosingPosition, s"Unknown end inclusive/exclusive specifier, got: '$other'")
     }
     currString = currString.substring(1)  // eat the inclusive/exclusive specifier
     currString = currString.dropWhile(_ == ' ')
@@ -90,6 +86,8 @@ class RangeTransform(val c: Context) {
       c.abort(c.enclosingPosition, s"Unused characters in range specifier: '$unused'")
     }
 
+    // TODO: FINISH THIS!
+
     c.warning(c.enclosingPosition, s"$startInclusive ${showRaw(minArg)} ${showRaw(maxArg)} $endInclusive")
 
     q""
diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index 797c75c4..d6c51704 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -25,7 +25,7 @@ import rangeMacroTest._
 @dump
 class RangeMacroTest extends ChiselPropSpec {
   property("Range macros should work") {
-    def ducks() = {2}
-    range"  (0, ${ducks}]   "
+    range"(0,${1+1}]"
+    range"  (  0  ,  ${1+1}  ]  "
   }
 }
-- 
cgit v1.2.3


From dd28ef5d95e49c2822f9e37e8011ceab69cad532 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 26 Oct 2016 14:48:00 -0700
Subject: Rename RangeMacro, remove nameprop deps

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index d6c51704..88a0730f 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -22,8 +22,7 @@ import rangeMacroTest._
   * Note: negative (failure) conditions can't be tested because they will fail at compile time,
   * before the testing environment is entered.
   */
-@dump
-class RangeMacroTest extends ChiselPropSpec {
+class RangeMacroSpec extends ChiselPropSpec {
   property("Range macros should work") {
     range"(0,${1+1}]"
     range"  (  0  ,  ${1+1}  ]  "
-- 
cgit v1.2.3


From bb1cb894f6f1c88e0d60de1501e86d68de7c0f76 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 15:57:06 -0800
Subject: first attack on creating a range api for chisel3

---
 .../src/main/scala/chisel3/core/Bits.scala         |  9 ++++
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 57 ++++++++++++++++++++++
 .../scala/chisel3/internal/RangeTransform.scala    |  3 +-
 3 files changed, 68 insertions(+), 1 deletion(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 4a09c70e..83733089 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -563,6 +563,10 @@ private[core] sealed trait UIntFactory {
     result.binding = LitBinding()
     result
   }
+   /** Create a UInt with the specified range */
+  def apply(range: Range): UInt = {
+    width(range.getWidth)
+  }
 
   /** Create a UInt with a specified width - compatibility with Chisel2. */
   // NOTE: This resolves UInt(width = 32)
@@ -728,6 +732,11 @@ object SInt {
   /** Create an SInt literal with specified width. */
   def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
+  /** Create a SInt with the specified range */
+  def apply(range: Range): SInt = {
+    width(range.getWidth)
+  }
+
   def Lit(value: BigInt): SInt = Lit(value, Width())
   def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
    /** Create an SInt literal with specified width. */
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 17b869f2..d463d78e 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -109,6 +109,63 @@ case class Index(imm: Arg, value: Arg) extends Arg {
   override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
 }
 
+object Range {
+  def log2Up(value: BigInt): Int = {
+    require(value >= 0)
+    1 max (value-1).bitLength
+  }
+}
+
+/*sealed abstract class Range {
+
+}*/
+sealed trait Bound
+sealed trait NumericBound[T] extends Bound {
+  val value: T
+}
+sealed case class Open[T](value: T) extends NumericBound[T]
+sealed case class Closed[T](value: T) extends NumericBound[T]
+
+sealed trait Range {
+  val min: Bound
+  val max: Bound
+  def getWidth: Width
+}
+
+sealed trait KnownIntRange extends Range {
+  val min: NumericBound[Int]
+  val max: NumericBound[Int]
+
+  require( (min, max) match {
+    case (low, Open(high_val)) => low.value < high_val
+    case (Open(low_val), high) => low_val < high.value
+    case (Closed(low_val), Closed(high_val)) => low_val <= high_val
+  })
+}
+
+sealed case class KnownUIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+  require (min.value >= 0)
+
+  def getWidth: Width = max match {
+    case Open(v) => Width(BigInt(v - 1).bitLength.max(1))
+    case Closed(v) => Width(BigInt(v).bitLength.max(1))
+  }
+}
+
+sealed case class KnownSIntRange(min: NumericBound[Int], max: NumericBound[Int]) extends KnownIntRange {
+
+  val maxWidth = max match {
+    case Open(v) => Width(BigInt(v - 1).bitLength + 1)
+    case Closed(v) => Width(BigInt(v).bitLength + 1)
+  }
+  val minWidth = min match {
+    case Open(v) => Width(BigInt(v + 1).bitLength + 1)
+    case Closed(v) => Width(BigInt(v).bitLength + 1)
+  }
+  def getWidth: Width = maxWidth.max(minWidth)
+
+}
+
 object Width {
   def apply(x: Int): Width = KnownWidth(x)
   def apply(): Width = UnknownWidth()
diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
index 20142d5d..ff5ba953 100644
--- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -90,6 +90,7 @@ class RangeTransform(val c: Context) {
 
     c.warning(c.enclosingPosition, s"$startInclusive ${showRaw(minArg)} ${showRaw(maxArg)} $endInclusive")
 
-    q""
+    q"_root_.chisel3.internal.firrtl"
+
   }
 }
-- 
cgit v1.2.3


From d46b9acd557d2fe6ffe27f43ee72cd9b2a22f65d Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 9 Nov 2016 16:03:21 -0800
Subject: Add bounds generation to range macro transform

---
 .../main/scala/chisel3/internal/RangeTransform.scala   | 18 ++++++++++++------
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
index ff5ba953..d90492cd 100644
--- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -86,11 +86,17 @@ class RangeTransform(val c: Context) {
       c.abort(c.enclosingPosition, s"Unused characters in range specifier: '$unused'")
     }
 
-    // TODO: FINISH THIS!
-
-    c.warning(c.enclosingPosition, s"$startInclusive ${showRaw(minArg)} ${showRaw(maxArg)} $endInclusive")
-
-    q"_root_.chisel3.internal.firrtl"
-
+    val startBound = if (startInclusive) {
+      q"_root_.chisel3.internal.firrtl.Closed($minArg)"
+    } else {
+      q"_root_.chisel3.internal.firrtl.Open($minArg)"
+    }
+    val endBound = if (endInclusive) {
+      q"_root_.chisel3.internal.firrtl.Closed($maxArg)"
+    } else {
+      q"_root_.chisel3.internal.firrtl.Open($maxArg)"
+    }
+    
+    q"($startBound, $endBound)"
   }
 }
-- 
cgit v1.2.3


From 22406a589c4a3f8de42a9f5c988201f474c11282 Mon Sep 17 00:00:00 2001
From: chick
Date: Wed, 9 Nov 2016 16:23:52 -0800
Subject: simple test that range interpolator works with UInt factory method

---
 chiselFrontend/src/main/scala/chisel3/core/Bits.scala | 10 +++++++++-
 src/main/scala/chisel3/package.scala                  |  7 +++++++
 src/test/scala/chiselTests/RangeMacroTest.scala       |  9 ---------
 src/test/scala/chiselTests/RangeSpec.scala            | 17 +++++++++++++++++
 4 files changed, 33 insertions(+), 10 deletions(-)
 create mode 100644 src/test/scala/chiselTests/RangeSpec.scala

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 83733089..82b60a4c 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -563,10 +563,14 @@ private[core] sealed trait UIntFactory {
     result.binding = LitBinding()
     result
   }
-   /** Create a UInt with the specified range */
+  /** Create a UInt with the specified range */
   def apply(range: Range): UInt = {
     width(range.getWidth)
   }
+  /** Create a UInt with the specified range */
+  def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
+    apply(KnownUIntRange(range._1, range._2))
+  }
 
   /** Create a UInt with a specified width - compatibility with Chisel2. */
   // NOTE: This resolves UInt(width = 32)
@@ -736,6 +740,10 @@ object SInt {
   def apply(range: Range): SInt = {
     width(range.getWidth)
   }
+  /** Create a SInt with the specified range */
+  def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
+    apply(KnownSIntRange(range._1, range._2))
+  }
 
   def Lit(value: BigInt): SInt = Lit(value, Width())
   def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 3cdda971..436534e1 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,3 +1,4 @@
+
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
@@ -11,6 +12,8 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   import chisel3.util._
   import chisel3.internal.firrtl.Port
 
+  import chisel3.internal.firrtl.NumericBound
+
   type Direction = chisel3.core.Direction
   val Input   = chisel3.core.Input
   val Output  = chisel3.core.Output
@@ -156,6 +159,10 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
   }
 
+  implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+    def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
+  }
+
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
index 88a0730f..cafff1d2 100644
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ b/src/test/scala/chiselTests/RangeMacroTest.scala
@@ -8,15 +8,6 @@ import org.scalatest._
 import org.scalatest.prop._
 import chisel3.testers.BasicTester
 
-package object rangeMacroTest {
-
-implicit class ChiselRange(val sc: StringContext) extends AnyVal {
-  def range(args: Any*): Unit = macro chisel3.internal.RangeTransform.apply
-}
-
-}
-
-import rangeMacroTest._
 
 /** Comprehensive test of static range parsing functionality.
   * Note: negative (failure) conditions can't be tested because they will fail at compile time,
diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
new file mode 100644
index 00000000..edaff8aa
--- /dev/null
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+package chiselTests
+
+import chisel3._
+import org.scalatest.{Matchers, FreeSpec}
+
+class RangeSpec extends FreeSpec with Matchers {
+  "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "to specify a UInt" in {
+      val x = UInt(range"[0, 7)")
+      x.getWidth should be (3)
+
+      println(range"[4,32)")
+    }
+ }
+}
-- 
cgit v1.2.3


From b39b08b6d489ab6d2dc9bb8a40a87c4ac5834828 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Wed, 9 Nov 2016 16:25:34 -0800
Subject: Delete RangeMacroTest now that RangeSpec exists.

---
 src/test/scala/chiselTests/RangeMacroTest.scala | 21 ---------------------
 1 file changed, 21 deletions(-)
 delete mode 100644 src/test/scala/chiselTests/RangeMacroTest.scala

diff --git a/src/test/scala/chiselTests/RangeMacroTest.scala b/src/test/scala/chiselTests/RangeMacroTest.scala
deleted file mode 100644
index cafff1d2..00000000
--- a/src/test/scala/chiselTests/RangeMacroTest.scala
+++ /dev/null
@@ -1,21 +0,0 @@
-// See LICENSE for license details.
-
-package chiselTests
-
-import chisel3._
-import scala.language.experimental.macros
-import org.scalatest._
-import org.scalatest.prop._
-import chisel3.testers.BasicTester
-
-
-/** Comprehensive test of static range parsing functionality.
-  * Note: negative (failure) conditions can't be tested because they will fail at compile time,
-  * before the testing environment is entered.
-  */
-class RangeMacroSpec extends ChiselPropSpec {
-  property("Range macros should work") {
-    range"(0,${1+1}]"
-    range"  (  0  ,  ${1+1}  ]  "
-  }
-}
-- 
cgit v1.2.3


From 87144822597c51fc010ab4aaca2db48904dce029 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Wed, 9 Nov 2016 16:57:26 -0800
Subject: Add some more tests.

---
 src/test/scala/chiselTests/RangeSpec.scala | 58 ++++++++++++++++++++++++++++--
 1 file changed, 56 insertions(+), 2 deletions(-)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index edaff8aa..b18e9d2a 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,10 +8,64 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "to specify a UInt" in {
-      val x = UInt(range"[0, 7)")
+      val x = UInt(range"[0, 8)")
       x.getWidth should be (3)
 
       println(range"[4,32)")
+
+      UInt(range"[0, 8]").getWidth should be (4)
+    }
+
+    "to specify an SInt" in {
+      SInt(range"[0, 8)").getWidth should be (4)
+
+      SInt(range"[0, 8]").getWidth should be (5)
+
+      SInt(range"[-4, 4)").getWidth should be (3)
+    }
+
+    "it should check that the range is valid for UInt" in {
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[1, 0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[-1, 1]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"[0,0)")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,0)")
+      }
+
+      UInt(range"[0, 0]").getWidth should be (1)
+    }
+
+    "it should check that the range is valid for SInt" in {
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"[1, 0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,0]")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"[0,0)")
+      }
+
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,0)")
+      }
+
+      SInt(range"[0, 0]").getWidth should be (1)
     }
- }
+  }
 }
-- 
cgit v1.2.3


From 9192dc67a0a3b2abb1914ea5472c33c944908a80 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:04:17 -0800
Subject: Incorporate feedback.

---
 src/test/scala/chiselTests/RangeSpec.scala | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index b18e9d2a..8734c4d5 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,12 +8,11 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "to specify a UInt" in {
-      val x = UInt(range"[0, 8)")
-      x.getWidth should be (3)
-
-      println(range"[4,32)")
+      UInt(range"[0, 8)").getWidth should be (3)
 
       UInt(range"[0, 8]").getWidth should be (4)
+
+      UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "to specify an SInt" in {
@@ -22,6 +21,8 @@ class RangeSpec extends FreeSpec with Matchers {
       SInt(range"[0, 8]").getWidth should be (5)
 
       SInt(range"[-4, 4)").getWidth should be (3)
+
+      SInt(range"[0, 0]").getWidth should be (1)
     }
 
     "it should check that the range is valid for UInt" in {
@@ -44,8 +45,6 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0)")
       }
-
-      UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "it should check that the range is valid for SInt" in {
@@ -64,8 +63,6 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0)")
       }
-
-      SInt(range"[0, 0]").getWidth should be (1)
     }
   }
 }
-- 
cgit v1.2.3


From 5499975f038eea469adfdd819d3727ea89686a39 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:13:14 -0800
Subject: Add a macro test case

---
 src/test/scala/chiselTests/RangeSpec.scala | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 8734c4d5..90189e0a 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -3,10 +3,33 @@
 package chiselTests
 
 import chisel3._
+import chisel3.internal.firrtl.{Open, Closed}
 import org.scalatest.{Matchers, FreeSpec}
 
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "range macros should allow open and closed bounds" in {
+      {
+        val (lo, hi) = range"[-1, 1)"
+        lo should be (Closed(-1))
+        hi should be (Open(1))
+      }
+      {
+        val (lo, hi) = range"[-1, 1]"
+        lo should be (Closed(-1))
+        hi should be (Closed(1))
+      }
+      {
+        val (lo, hi) = range"(-1, 1]"
+        lo should be (Open(-1))
+        hi should be (Closed(1))
+      }
+      {
+        val (lo, hi) = range"(-1, 1)"
+        lo should be (Open(-1))
+        hi should be (Open(1))
+      }
+    }
     "to specify a UInt" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
-- 
cgit v1.2.3


From 657befd9f948e54bf17f5d5f7fcacae96f93e86d Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:15:35 -0800
Subject: Change some of the test names.

---
 src/test/scala/chiselTests/RangeSpec.scala | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 90189e0a..15b3092b 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -30,7 +30,7 @@ class RangeSpec extends FreeSpec with Matchers {
         hi should be (Open(1))
       }
     }
-    "to specify a UInt" in {
+    "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
       UInt(range"[0, 8]").getWidth should be (4)
@@ -38,7 +38,7 @@ class RangeSpec extends FreeSpec with Matchers {
       UInt(range"[0, 0]").getWidth should be (1)
     }
 
-    "to specify an SInt" in {
+    "SInt should get the correct width from a range" in {
       SInt(range"[0, 8)").getWidth should be (4)
 
       SInt(range"[0, 8]").getWidth should be (5)
@@ -48,7 +48,7 @@ class RangeSpec extends FreeSpec with Matchers {
       SInt(range"[0, 0]").getWidth should be (1)
     }
 
-    "it should check that the range is valid for UInt" in {
+    "UInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[1, 0]")
       }
@@ -70,7 +70,7 @@ class RangeSpec extends FreeSpec with Matchers {
       }
     }
 
-    "it should check that the range is valid for SInt" in {
+    "SInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[1, 0]")
       }
-- 
cgit v1.2.3


From 02721d45f5261eac8d8eb6e260497a13aaa3692b Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:23:49 -0800
Subject: Add interpolated variables to range macro test.

---
 src/test/scala/chiselTests/RangeSpec.scala | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 15b3092b..25d963a1 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -30,6 +30,14 @@ class RangeSpec extends FreeSpec with Matchers {
         hi should be (Open(1))
       }
     }
+    "range macros should work with interpolated variables" in {
+      val a = 10
+      val b = -3
+
+      range"[$b, $a)" should be( (Closed(b), Open(a)) )
+
+      range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
+    }
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
 
-- 
cgit v1.2.3


From fdc61a258695d64b7716ae6bec6a37cabfb875bb Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:25:40 -0800
Subject: Write range macro tests in a better way.

---
 src/test/scala/chiselTests/RangeSpec.scala | 27 +++++++--------------------
 1 file changed, 7 insertions(+), 20 deletions(-)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 25d963a1..84db9b57 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -9,26 +9,13 @@ import org.scalatest.{Matchers, FreeSpec}
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
     "range macros should allow open and closed bounds" in {
-      {
-        val (lo, hi) = range"[-1, 1)"
-        lo should be (Closed(-1))
-        hi should be (Open(1))
-      }
-      {
-        val (lo, hi) = range"[-1, 1]"
-        lo should be (Closed(-1))
-        hi should be (Closed(1))
-      }
-      {
-        val (lo, hi) = range"(-1, 1]"
-        lo should be (Open(-1))
-        hi should be (Closed(1))
-      }
-      {
-        val (lo, hi) = range"(-1, 1)"
-        lo should be (Open(-1))
-        hi should be (Open(1))
-      }
+      range"[-1, 1)" should be( (Closed(-1), Open(1)) )
+
+      range"[-1, 1]" should be( (Closed(-1), Closed(1)) )
+
+      range"(-1, 1]" should be( (Open(-1), Closed(1)) )
+
+      range"(-1, 1)" should be( (Open(-1), Open(1)) )
     }
     "range macros should work with interpolated variables" in {
       val a = 10
-- 
cgit v1.2.3


From c9849a59d5ea0315096ff5f90db22ce39c7f4cc5 Mon Sep 17 00:00:00 2001
From: Paul Rigge
Date: Thu, 10 Nov 2016 15:31:12 -0800
Subject: Oops, forgot to include literal expressions.

---
 src/test/scala/chiselTests/RangeSpec.scala | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 84db9b57..509ed82e 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -24,6 +24,8 @@ class RangeSpec extends FreeSpec with Matchers {
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
 
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
+
+      range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
     }
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
-- 
cgit v1.2.3


From 2db9bc81015000b5ee4581dc57c0f339ae9f9329 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 14:15:37 -0800
Subject: Add invalid range specifier test

---
 src/test/scala/chiselTests/RangeSpec.scala | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 509ed82e..cbac4d4c 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -84,5 +84,18 @@ class RangeSpec extends FreeSpec with Matchers {
         SInt(range"(0,0)")
       }
     }
+
+    "Invalid range specifiers should fail at compile time" in {
+      assertDoesNotCompile(""" range"" """)
+      assertDoesNotCompile(""" range"[]" """)
+      assertDoesNotCompile(""" range"0" """)
+      assertDoesNotCompile(""" range"[0]" """)
+      assertDoesNotCompile(""" range"[0, 1" """)
+      assertDoesNotCompile(""" range"0, 1]" """)
+      assertDoesNotCompile(""" range"[0, 1, 2]" """)
+      assertDoesNotCompile(""" range"[a]" """)
+      assertDoesNotCompile(""" range"[a, b]" """)
+      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+    }
   }
 }
-- 
cgit v1.2.3


From 876bc32feca6bd0a2aaec7019fd3d29675ce0255 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 15:23:36 -0800
Subject: Fix open-open range specifier, remove dead code, restyle tests

---
 .../main/scala/chisel3/internal/firrtl/IR.scala    | 15 ++----
 src/main/scala/chisel3/package.scala               |  5 +-
 src/test/scala/chiselTests/RangeSpec.scala         | 58 +++++++++++-----------
 3 files changed, 32 insertions(+), 46 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index d463d78e..262b939f 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -109,16 +109,6 @@ case class Index(imm: Arg, value: Arg) extends Arg {
   override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[${value.fullName(ctx)}]"
 }
 
-object Range {
-  def log2Up(value: BigInt): Int = {
-    require(value >= 0)
-    1 max (value-1).bitLength
-  }
-}
-
-/*sealed abstract class Range {
-
-}*/
 sealed trait Bound
 sealed trait NumericBound[T] extends Bound {
   val value: T
@@ -137,8 +127,9 @@ sealed trait KnownIntRange extends Range {
   val max: NumericBound[Int]
 
   require( (min, max) match {
-    case (low, Open(high_val)) => low.value < high_val
-    case (Open(low_val), high) => low_val < high.value
+    case (Open(low_val), Open(high_val)) => low_val < high_val - 1
+    case (Closed(low_val), Open(high_val)) => low_val < high_val
+    case (Open(low_val), Closed(high_val)) => low_val < high_val
     case (Closed(low_val), Closed(high_val)) => low_val <= high_val
   })
 }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 436534e1..b49f6dec 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,10 +1,9 @@
-
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
   import scala.language.experimental.macros
 
-  import internal.firrtl.Width
+  import internal.firrtl.{Width, NumericBound}
   import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
@@ -12,8 +11,6 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   import chisel3.util._
   import chisel3.internal.firrtl.Port
 
-  import chisel3.internal.firrtl.NumericBound
-
   type Direction = chisel3.core.Direction
   val Input   = chisel3.core.Input
   val Output  = chisel3.core.Output
diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index cbac4d4c..565d304d 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -8,40 +8,52 @@ import org.scalatest.{Matchers, FreeSpec}
 
 class RangeSpec extends FreeSpec with Matchers {
   "Ranges can be specified for UInt, SInt, and FixedPoint" - {
+    "invalid range specifiers should fail at compile time" in {
+      assertDoesNotCompile(""" range"" """)
+      assertDoesNotCompile(""" range"[]" """)
+      assertDoesNotCompile(""" range"0" """)
+      assertDoesNotCompile(""" range"[0]" """)
+      assertDoesNotCompile(""" range"[0, 1" """)
+      assertDoesNotCompile(""" range"0, 1]" """)
+      assertDoesNotCompile(""" range"[0, 1, 2]" """)
+      assertDoesNotCompile(""" range"[a]" """)
+      assertDoesNotCompile(""" range"[a, b]" """)
+      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+    }
+
     "range macros should allow open and closed bounds" in {
       range"[-1, 1)" should be( (Closed(-1), Open(1)) )
-
       range"[-1, 1]" should be( (Closed(-1), Closed(1)) )
-
       range"(-1, 1]" should be( (Open(-1), Closed(1)) )
-
       range"(-1, 1)" should be( (Open(-1), Open(1)) )
     }
+
+    "range specifiers should be whitespace tolerant" in {
+      range"[-1,1)" should be( (Closed(-1), Open(1)) )
+      range" [-1,1) " should be( (Closed(-1), Open(1)) )
+      range" [ -1 , 1 ) " should be( (Closed(-1), Open(1)) )
+      range"   [   -1   ,   1   )   " should be( (Closed(-1), Open(1)) )
+    }
+
     "range macros should work with interpolated variables" in {
       val a = 10
       val b = -3
 
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
-
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
-
       range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
     }
+
     "UInt should get the correct width from a range" in {
       UInt(range"[0, 8)").getWidth should be (3)
-
       UInt(range"[0, 8]").getWidth should be (4)
-
       UInt(range"[0, 0]").getWidth should be (1)
     }
 
     "SInt should get the correct width from a range" in {
       SInt(range"[0, 8)").getWidth should be (4)
-
       SInt(range"[0, 8]").getWidth should be (5)
-
       SInt(range"[-4, 4)").getWidth should be (3)
-
       SInt(range"[0, 0]").getWidth should be (1)
     }
 
@@ -49,53 +61,39 @@ class RangeSpec extends FreeSpec with Matchers {
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[1, 0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[-1, 1]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"[0,0)")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         UInt(range"(0,0)")
       }
+      an [IllegalArgumentException] should be thrownBy {
+        UInt(range"(0,1)")
+      }
     }
 
     "SInt should check that the range is valid" in {
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[1, 0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0]")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"[0,0)")
       }
-
       an [IllegalArgumentException] should be thrownBy {
         SInt(range"(0,0)")
       }
-    }
-
-    "Invalid range specifiers should fail at compile time" in {
-      assertDoesNotCompile(""" range"" """)
-      assertDoesNotCompile(""" range"[]" """)
-      assertDoesNotCompile(""" range"0" """)
-      assertDoesNotCompile(""" range"[0]" """)
-      assertDoesNotCompile(""" range"[0, 1" """)
-      assertDoesNotCompile(""" range"0, 1]" """)
-      assertDoesNotCompile(""" range"[0, 1, 2]" """)
-      assertDoesNotCompile(""" range"[a]" """)
-      assertDoesNotCompile(""" range"[a, b]" """)
-      assertCompiles(""" range"[0, 1]" """)  // syntax sanity check
+      an [IllegalArgumentException] should be thrownBy {
+        SInt(range"(0,1)")
+      }
     }
   }
 }
-- 
cgit v1.2.3


From fffde2bfbffeacbe9cca68d539b199bd18e30294 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 16:35:06 -0800
Subject: Address review comments

---
 coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala | 6 +++---
 src/test/scala/chiselTests/RangeSpec.scala                      | 3 +++
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
index d90492cd..f431341d 100644
--- a/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
+++ b/coreMacros/src/main/scala/chisel3/internal/RangeTransform.scala
@@ -29,7 +29,7 @@ class RangeTransform(val c: Context) {
       */
     def getNextValue(): c.Tree = {
       currString = currString.dropWhile(_ == ' ')  // allow whitespace
-      if (currString.isEmpty()) {
+      if (currString.isEmpty) {
         if (nextArgIndex >= args.length) {
           c.abort(c.enclosingPosition, s"Incomplete range specifier")
         }
@@ -46,7 +46,7 @@ class RangeTransform(val c: Context) {
       } else {
         val nextStringVal = currString.takeWhile(!Set('[', '(', ' ', ',', ')', ']').contains(_))
         currString = currString.substring(nextStringVal.length)
-        if (currString.isEmpty()) {
+        if (currString.isEmpty) {
           c.abort(c.enclosingPosition, s"Incomplete range specifier")
         }
         c.parse(nextStringVal)
@@ -96,7 +96,7 @@ class RangeTransform(val c: Context) {
     } else {
       q"_root_.chisel3.internal.firrtl.Open($maxArg)"
     }
-    
+
     q"($startBound, $endBound)"
   }
 }
diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 565d304d..60ececbe 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -42,6 +42,9 @@ class RangeSpec extends FreeSpec with Matchers {
       range"[$b, $a)" should be( (Closed(b), Open(a)) )
       range"[${a + b}, $a)" should be( (Closed(a + b), Open(a)) )
       range"[${-3 - 7}, ${-3 + a})" should be( (Closed(-10), Open(-3 + a)) )
+
+      def number(n: Int): Int = n
+      range"[${number(1)}, ${number(3)})" should be( (Closed(1), Open(3)) )
     }
 
     "UInt should get the correct width from a range" in {
-- 
cgit v1.2.3


From e8aea3f4153b58321784ac33734305207570ef75 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 17:51:56 -0800
Subject: Move ChiselRange to experimental

---
 src/main/scala/chisel3/package.scala       | 16 ++++++++++++----
 src/test/scala/chiselTests/RangeSpec.scala |  2 ++
 2 files changed, 14 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index b49f6dec..29aa6528 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -156,10 +156,6 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
   }
 
-  implicit class ChiselRange(val sc: StringContext) extends AnyVal {
-    def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
-  }
-
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
@@ -206,5 +202,17 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     implicit def fromBigIntToIntParam(x: BigInt): IntParam = IntParam(x)
     implicit def fromDoubleToDoubleParam(x: Double): DoubleParam = DoubleParam(x)
     implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
+
+    implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+      /** Specifies a range using mathematical range notation. Variables can be interpolated using
+       *  standard string interpolation syntax.
+        * @example {{{
+        * UInt(range"[0, 2)")
+        * UInt(range"[0, $myInt)")
+        * UInt(range"[0, ${myInt + 2})")
+        * }}}
+        */
+      def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
+    }
   }
 }
diff --git a/src/test/scala/chiselTests/RangeSpec.scala b/src/test/scala/chiselTests/RangeSpec.scala
index 60ececbe..e2313f34 100644
--- a/src/test/scala/chiselTests/RangeSpec.scala
+++ b/src/test/scala/chiselTests/RangeSpec.scala
@@ -3,6 +3,8 @@
 package chiselTests
 
 import chisel3._
+import chisel3.experimental.ChiselRange
+
 import chisel3.internal.firrtl.{Open, Closed}
 import org.scalatest.{Matchers, FreeSpec}
 
-- 
cgit v1.2.3


From 15a8d3818a1b185051b260ffc82da1fb4a60a45e Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:31:24 -0800
Subject: Break out deprecated literal constructors, refactor all the things!

---
 .../src/main/scala/chisel3/core/Aggregate.scala    | 10 +--
 .../src/main/scala/chisel3/core/Bits.scala         | 69 +++++------------
 .../src/main/scala/chisel3/core/Mem.scala          |  2 +-
 .../src/main/scala/chisel3/core/SeqUtils.scala     |  4 +-
 .../src/main/scala/chisel3/core/package.scala      | 50 ++++++++++++
 src/main/scala/chisel3/compatibility.scala         | 88 +++++++++++-----------
 src/main/scala/chisel3/package.scala               | 88 +++++++++++-----------
 7 files changed, 167 insertions(+), 144 deletions(-)
 create mode 100644 chiselFrontend/src/main/scala/chisel3/core/package.scala

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index de7af462..77a1b57a 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -123,10 +123,10 @@ object Vec {
   /** Truncate an index to implement modulo-power-of-2 addressing. */
   private[core] def truncateIndex(idx: UInt, n: Int)(implicit sourceInfo: SourceInfo): UInt = {
     val w = BigInt(n-1).bitLength
-    if (n <= 1) UInt(0)
+    if (n <= 1) 0.U
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w-1,0)
-    else (idx | UInt(0, w))(w-1,0)
+    else (idx | 0.U(w))(w-1,0)
   }
 }
 
@@ -249,7 +249,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   // IndexedSeq has its own hashCode/equals that we must not use
   override def hashCode: Int = super[HasId].hashCode
   override def equals(that: Any): Boolean = super[HasId].equals(that)
-  
+
   @deprecated("Use Vec.apply instead", "chisel3")
   def read(idx: UInt): T
 
@@ -288,7 +288,7 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   /** Helper function that appends an index (literal value) to each element,
     * useful for hardware generators which output an index.
     */
-  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => UInt(i))
+  private def indexWhereHelper(p: T => Bool) = this map p zip (0 until length).map(i => i.asUInt)
 
   /** Outputs the index of the first element for which p outputs true.
     */
@@ -388,7 +388,7 @@ class Bundle extends Aggregate {
   private[chisel3] lazy val flatten = namedElts.flatMap(_._2.flatten)
   private[chisel3] override def _onModuleClose: Unit = // scalastyle:ignore method.name
     for ((name, elt) <- namedElts) { elt.setRef(this, _namespace.name(name)) }
-    
+
   private[chisel3] final def allElements: Seq[Element] = namedElts.flatMap(_._2.allElements)
 
   override def cloneType : this.type = {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 82b60a4c..1d3f9243 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     }
     val w = x - y + 1
     if (isLit()) {
-      UInt((litValue >> y) & ((BigInt(1) << w) - 1), w)
+      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w)
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
@@ -304,11 +304,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
   final def toPrintable: Printable = Decimal(this)
 }
 
-/** Provides a set of operations to create UInt types and literals.
-  * Identical in functionality to the UInt companion object.
-  */
-object Bits extends UIntFactory
-
 // REVIEW TODO: Further discussion needed on what Num actually is.
 /** Abstract trait defining operations available on numeric-like wire data
   * types.
@@ -408,14 +403,14 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   private[chisel3] def toType = s"UInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    UInt(value, width).asInstanceOf[this.type]
+    value.asUInt(width).asInstanceOf[this.type]
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
 
-  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = UInt(0) - this
-  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = UInt(0) -% this
+  def do_unary_- (implicit sourceInfo: SourceInfo) : UInt = 0.U - this
+  def do_unary_-% (implicit sourceInfo: SourceInfo): UInt = 0.U -% this
 
   override def do_+ (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this +% that
   override def do_- (that: UInt)(implicit sourceInfo: SourceInfo): UInt = this -% that
@@ -463,8 +458,8 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def andR(): Bool = macro SourceInfoTransform.noArg
   final def xorR(): Bool = macro SourceInfoTransform.noArg
 
-  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != UInt(0)
-  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === UInt(0)
+  def do_orR(implicit sourceInfo: SourceInfo): Bool = this != 0.U
+  def do_andR(implicit sourceInfo: SourceInfo): Bool = ~this === 0.U
   def do_xorR(implicit sourceInfo: SourceInfo): Bool = redop(sourceInfo, XorReduceOp)
 
   override def do_< (that: UInt)(implicit sourceInfo: SourceInfo): Bool = compop(sourceInfo, LessOp, that)
@@ -483,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === UInt(0, 1)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -501,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset
 
   def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = {
-    val bit = UInt(1, 1) << off
+    val bit = 1.U(1) << off
     Mux(dat, this | bit, ~(~this | bit))
   }
 
@@ -532,31 +527,20 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 }
 
 // This is currently a factory because both Bits and UInt inherit it.
-private[core] sealed trait UIntFactory {
+trait UIntFactory {
   /** Create a UInt type with inferred width. */
   def apply(): UInt = apply(Width())
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
-  /** Create a UInt with a specified width - compatibility with Chisel2. */
-  def width(width: Int): UInt = apply(Width(width))
-  /** Create a UInt port with specified width. */
-  def width(width: Width): UInt = new UInt(width)
-  /** Create a UInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
-  /** Create a UInt literal with inferred width. */
-  def apply(n: String): UInt = Lit(n)
-   /** Create a UInt literal with fixed width. */
-  def apply(n: String, width: Int): UInt = Lit(parse(n), width)
-  /** Create a UInt literal with specified width. */
-  def apply(value: BigInt, width: Width): UInt = Lit(value, width)
-  def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+  protected[chisel3] def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
    /** Create a UInt literal with inferred width. */
-  def Lit(value: BigInt): UInt = Lit(value, Width())
-  def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
+  protected[chisel3] def Lit(value: BigInt): UInt = Lit(value, Width())
+  protected[chisel3] def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
    /** Create a UInt literal with fixed width. */
-  def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
+  protected[chisel3] def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
    /** Create a UInt literal with specified width. */
-  def Lit(value: BigInt, width: Width): UInt = {
+  protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
     val result = new UInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -572,25 +556,7 @@ private[core] sealed trait UIntFactory {
     apply(KnownUIntRange(range._1, range._2))
   }
 
-  /** Create a UInt with a specified width - compatibility with Chisel2. */
-  // NOTE: This resolves UInt(width = 32)
-  def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
-  /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-  def apply(value: BigInt): UInt = apply(value, Width())
-  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
-  /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-  def apply(dir: Direction): UInt = apply(dir, Width())
-  def apply(dir: Direction, wWidth: Width): UInt = {
-    val result = apply(wWidth)
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
-
-  private def parse(n: String) = {
+  protected def parse(n: String) = {
     val (base, num) = n.splitAt(1)
     val radix = base match {
       case "x" | "h" => 16
@@ -602,7 +568,7 @@ private[core] sealed trait UIntFactory {
     BigInt(num.filterNot(_ == '_'), radix)
   }
 
-  private def parsedWidth(n: String) =
+  protected def parsedWidth(n: String) =
     if (n(0) == 'b') {
       Width(n.length-1)
     } else if (n(0) == 'h') {
@@ -613,6 +579,7 @@ private[core] sealed trait UIntFactory {
 }
 
 object UInt extends UIntFactory
+object Bits extends UIntFactory
 
 sealed class SInt private (width: Width, lit: Option[SLit] = None)
     extends Bits(width, lit) with Num[SInt] {
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
index a43b19fe..1863e921 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Mem.scala
@@ -40,7 +40,7 @@ sealed abstract class MemBase[T <: Data](t: T, val length: Int) extends HasId wi
     */
   def apply(idx: Int): T = {
     require(idx >= 0 && idx < length)
-    apply(UInt(idx))
+    apply(idx.asUInt)
   }
 
   /** Creates a read/write accessor into the memory with dynamic addressing.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index 558dea7a..da4f2d94 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -30,7 +30,7 @@ private[chisel3] object SeqUtils {
   def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
 
   def do_count(in: Seq[Bool])(implicit sourceInfo: SourceInfo): UInt = in.size match {
-    case 0 => UInt(0)
+    case 0 => 0.U
     case 1 => in.head
     case n => count(in take n/2) +& count(in drop n/2)
   }
@@ -57,7 +57,7 @@ private[chisel3] object SeqUtils {
     if (in.tail.isEmpty) {
       in.head._2
     } else {
-      val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, UInt(0))
+      val masked = for ((s, i) <- in) yield Mux(s, i.asUInt, 0.U)
       val width = in.map(_._2.width).reduce(_ max _)
       in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
     }
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
new file mode 100644
index 00000000..46dfbe20
--- /dev/null
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -0,0 +1,50 @@
+package chisel3 {
+  package object core {
+    import internal.firrtl.Width
+
+    /**
+    * These implicit classes allow one to convert scala.Int|scala.BigInt to
+    * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
+    * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
+    * mark a width for the new literal.
+    *
+    * Also provides .asBool to scala.Boolean and .asUInt to String
+    *
+    * Note that, for stylistic reasons, one should avoid extracting immediately
+    * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
+    * confusion (the 1 is a bit length and the 0 is a bit extraction position).
+    * Prefer storing the result and then extracting from it.
+    */
+    implicit class fromIntToLiteral(val x: Int) {
+      def U: UInt = UInt.Lit(BigInt(x), Width())    // scalastyle:ignore method.name
+      def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
+
+      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asSInt(): SInt = SInt(x, Width())
+      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asSInt(width: Int): SInt = SInt(x, width)
+    }
+
+    implicit class fromBigIntToLiteral(val x: BigInt) {
+      def U: UInt = UInt.Lit(x, Width())       // scalastyle:ignore method.name
+      def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
+
+      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asSInt(): SInt = SInt(x, Width())
+      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asSInt(width: Int): SInt = SInt(x, width)
+    }
+
+    implicit class fromStringToLiteral(val x: String) {
+      def U: UInt = UInt.Lit(x)       // scalastyle:ignore method.name
+    }
+
+    implicit class fromBooleanToLiteral(val x: Boolean) {
+      def B: Bool = Bool(x)       // scalastyle:ignore method.name
+    }
+
+    implicit class fromDoubleToLiteral(val x: Double) {
+      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index d0d2ddb4..7157b4d4 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -6,6 +6,7 @@
 package object Chisel {     // scalastyle:ignore package.object.name
   implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict
   type Direction = chisel3.core.Direction
+
   val INPUT = chisel3.core.Direction.Input
   val OUTPUT = chisel3.core.Direction.Output
   val NODIR = chisel3.core.Direction.Unspecified
@@ -38,12 +39,51 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val assert = chisel3.core.assert
   val stop = chisel3.core.stop
 
+  trait UIntFactory extends chisel3.core.UIntFactory {
+    import chisel3.internal.firrtl.Width
+
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
+    /** Create a UInt literal with inferred width. */
+    def apply(n: String): UInt = Lit(n)
+    /** Create a UInt literal with fixed width. */
+    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+
+    /** Create a UInt literal with specified width. */
+    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+
+    /** Create a UInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+    /** Create a UInt with a specified width - compatibility with Chisel2. */
+    // NOTE: This resolves UInt(width = 32)
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    def apply(value: BigInt): UInt = apply(value, Width())
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): UInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): UInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+
+    /** Create a UInt port with specified width. */
+    def width(width: Width): UInt = apply(width)
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
-  val Bits = chisel3.core.Bits
+  object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
-  val UInt = chisel3.core.UInt
+  object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
   val SInt = chisel3.core.SInt
   type Bool = chisel3.core.Bool
@@ -68,46 +108,10 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
-  import chisel3.internal.firrtl.Width
-  /**
-  * These implicit classes allow one to convert scala.Int|scala.BigInt to
-  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
-  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
-  * mark a width for the new literal.
-  *
-  * Also provides .asBool to scala.Boolean and .asUInt to String
-  *
-  * Note that, for stylistic reasons, one should avoid extracting immediately
-  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
-  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
-  * Prefer storing the result and then extracting from it.
-  */
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())       // scalastyle:ignore method.name
-    def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)       // scalastyle:ignore method.name
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)       // scalastyle:ignore method.name
-  }
-
+  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 29aa6528..07dcdaca 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -31,10 +31,48 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
-  val Bits = chisel3.core.Bits
+
+  trait UIntFactory extends chisel3.core.UIntFactory {
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
+    /** Create a UInt literal with inferred width. */
+    def apply(n: String): UInt = Lit(n)
+    /** Create a UInt literal with fixed width. */
+    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+
+    /** Create a UInt literal with specified width. */
+    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+
+    /** Create a UInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+
+    /** Create a UInt with a specified width - compatibility with Chisel2. */
+    // NOTE: This resolves UInt(width = 32)
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    def apply(value: BigInt): UInt = apply(value, Width())
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): UInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): UInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => Input(result)
+        case chisel3.core.Direction.Output => Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+
+    /** Create a UInt port with specified width. */
+    def width(width: Width): UInt = apply(width)
+  }
+
+  object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
-  val UInt = chisel3.core.UInt
+  object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
   val SInt = chisel3.core.SInt
   type FixedPoint = chisel3.core.FixedPoint
@@ -113,48 +151,12 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   implicit def string2Printable(str: String): Printable = PString(str)
 
-  /**
-  * These implicit classes allow one to convert scala.Int|scala.BigInt to
-  * Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
-  * The versions .asUInt(width)|.asSInt(width) are also available to explicitly
-  * mark a width for the new literal.
-  *
-  * Also provides .asBool to scala.Boolean and .asUInt to String
-  *
-  * Note that, for stylistic reasons, one should avoid extracting immediately
-  * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
-  * confusion (the 1 is a bit length and the 0 is a bit extraction position).
-  * Prefer storing the result and then extracting from it.
-  */
-  implicit class fromIntToLiteral(val x: Int) extends AnyVal {
-    def U: UInt = UInt(BigInt(x), Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
+  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
 
-  implicit class fromBigIntToLiteral(val x: BigInt) extends AnyVal {
-    def U: UInt = UInt(x, Width())    // scalastyle:ignore method.name
-    def S: SInt = SInt(x, Width())    // scalastyle:ignore method.name
-
-    def asUInt(): UInt = UInt(x, Width())
-    def asSInt(): SInt = SInt(x, Width())
-    def asUInt(width: Int): UInt = UInt(x, width)
-    def asSInt(width: Int): SInt = SInt(x, width)
-  }
-  implicit class fromStringToLiteral(val x: String) extends AnyVal {
-    def U: UInt = UInt(x)    // scalastyle:ignore method.name
-  }
-  implicit class fromBooleanToLiteral(val x: Boolean) extends AnyVal {
-    def B: Bool = Bool(x)    // scalastyle:ignore method.name
-  }
-
-  implicit class fromDoubleToLiteral(val x: Double) extends AnyVal {
-    def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
-  }
 
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
-- 
cgit v1.2.3


From e0b277a40693476247a68e7c52672b547d7ceb17 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:47:36 -0800
Subject: Deprecate things, split more things

---
 .../src/main/scala/chisel3/core/Bits.scala         | 30 ++-----------------
 .../src/main/scala/chisel3/core/package.scala      | 33 ++++++++++++++++++---
 src/main/scala/chisel3/compatibility.scala         | 12 ++++----
 src/main/scala/chisel3/package.scala               | 34 ++++++++++------------
 4 files changed, 54 insertions(+), 55 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 1d3f9243..70da27fc 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -533,12 +533,6 @@ trait UIntFactory {
   /** Create a UInt port with specified width. */
   def apply(width: Width): UInt = new UInt(width)
 
-  protected[chisel3] def Lit(value: BigInt, width: Int): UInt = Lit(value, Width(width))
-   /** Create a UInt literal with inferred width. */
-  protected[chisel3] def Lit(value: BigInt): UInt = Lit(value, Width())
-  protected[chisel3] def Lit(n: String): UInt = Lit(parse(n), parsedWidth(n))
-   /** Create a UInt literal with fixed width. */
-  protected[chisel3] def Lit(n: String, width: Int): UInt = Lit(parse(n), width)
    /** Create a UInt literal with specified width. */
   protected[chisel3] def Lit(value: BigInt, width: Width): UInt = {
     val lit = ULit(value, width)
@@ -547,35 +541,15 @@ trait UIntFactory {
     result.binding = LitBinding()
     result
   }
+
   /** Create a UInt with the specified range */
   def apply(range: Range): UInt = {
-    width(range.getWidth)
+    apply(range.getWidth)
   }
   /** Create a UInt with the specified range */
   def apply(range: (NumericBound[Int], NumericBound[Int])): UInt = {
     apply(KnownUIntRange(range._1, range._2))
   }
-
-  protected def parse(n: String) = {
-    val (base, num) = n.splitAt(1)
-    val radix = base match {
-      case "x" | "h" => 16
-      case "d" => 10
-      case "o" => 8
-      case "b" => 2
-      case _ => Builder.error(s"Invalid base $base"); 2
-    }
-    BigInt(num.filterNot(_ == '_'), radix)
-  }
-
-  protected def parsedWidth(n: String) =
-    if (n(0) == 'b') {
-      Width(n.length-1)
-    } else if (n(0) == 'h') {
-      Width((n.length-1) * 4)
-    } else {
-      Width()
-    }
 }
 
 object UInt extends UIntFactory
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 46dfbe20..554e6238 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -1,4 +1,6 @@
 package chisel3 {
+  import internal.Builder
+
   package object core {
     import internal.firrtl.Width
 
@@ -21,8 +23,8 @@ package chisel3 {
 
       def asUInt(): UInt = UInt.Lit(x, Width())
       def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, width)
-      def asSInt(width: Int): SInt = SInt(x, width)
+      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      def asSInt(width: Int): SInt = SInt(x, Width(width))
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
@@ -31,12 +33,35 @@ package chisel3 {
 
       def asUInt(): UInt = UInt.Lit(x, Width())
       def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, width)
+      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
       def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
-      def U: UInt = UInt.Lit(x)       // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+    }
+
+    object fromStringToLiteral {
+      def parse(n: String) = {
+        val (base, num) = n.splitAt(1)
+        val radix = base match {
+          case "x" | "h" => 16
+          case "d" => 10
+          case "o" => 8
+          case "b" => 2
+          case _ => Builder.error(s"Invalid base $base"); 2
+        }
+        BigInt(num.filterNot(_ == '_'), radix)
+      }
+
+      def parsedWidth(n: String) =
+        if (n(0) == 'b') {
+          Width(n.length-1)
+        } else if (n(0) == 'h') {
+          Width((n.length-1) * 4)
+        } else {
+          Width()
+        }
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 7157b4d4..ac0caa45 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -42,13 +42,12 @@ package object Chisel {     // scalastyle:ignore package.object.name
   trait UIntFactory extends chisel3.core.UIntFactory {
     import chisel3.internal.firrtl.Width
 
-    /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
-
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(n)
+    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        Width(width))
 
     /** Create a UInt literal with specified width. */
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
@@ -74,6 +73,9 @@ package object Chisel {     // scalastyle:ignore package.object.name
       }
     }
 
+    /** Create a UInt with a specified width */
+    def width(width: Int): UInt = apply(Width(width))
+
     /** Create a UInt port with specified width. */
     def width(width: Width): UInt = apply(width)
   }
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 07dcdaca..84a4779e 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -33,39 +33,37 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Bits = chisel3.core.Bits
 
   trait UIntFactory extends chisel3.core.UIntFactory {
-    /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
-
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(n)
+    @deprecated("chisel3, will be removed by end of 2016, use n.U")
+    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(parse(n), width)
+    @deprecated("chisel3, will be removed by end of 2016, use n.U(width: Width)")
+    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
+        Width(width))
 
     /** Create a UInt literal with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    // NOTE: This resolves UInt(width = 32)
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.U")
     def apply(value: BigInt): UInt = apply(value, Width())
-    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
-    /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-    def apply(dir: Direction): UInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): UInt = {
-      val result = apply(wWidth)
-      dir match {
-        case chisel3.core.Direction.Input => Input(result)
-        case chisel3.core.Direction.Output => Output(result)
-        case chisel3.core.Direction.Unspecified => result
-      }
-    }
+
+    /** Create a UInt with a specified width */
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
     def width(width: Width): UInt = apply(width)
   }
 
-- 
cgit v1.2.3


From 9e32a39bda3fba11e6b0990e6ad5e7e17b5d8364 Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 16 Nov 2016 18:54:44 -0800
Subject: Refactor SInt WIP

---
 .../src/main/scala/chisel3/core/Bits.scala         | 36 +++----------------
 src/main/scala/chisel3/compatibility.scala         | 39 +++++++++++++++++++--
 src/main/scala/chisel3/package.scala               | 40 ++++++++++++++++++----
 3 files changed, 73 insertions(+), 42 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 70da27fc..7e467b88 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -555,7 +555,7 @@ trait UIntFactory {
 object UInt extends UIntFactory
 object Bits extends UIntFactory
 
-sealed class SInt private (width: Width, lit: Option[SLit] = None)
+sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
     extends Bits(width, lit) with Num[SInt] {
 
   private[core] override def cloneTypeWidth(w: Width): this.type =
@@ -659,37 +659,23 @@ sealed class SInt private (width: Width, lit: Option[SLit] = None)
   }
 }
 
-object SInt {
+trait SIntFactory {
   /** Create an SInt type with inferred width. */
   def apply(): SInt = apply(Width())
   /** Create a SInt type or port with fixed width. */
   def apply(width: Width): SInt = new SInt(width)
-  /** Create a SInt type or port with fixed width. */
-  def width(width: Int): SInt = apply(Width(width))
-  /** Create an SInt type with specified width. */
-  def width(width: Width): SInt = new SInt(width)
-
-  /** Create an SInt literal with inferred width. */
-  def apply(value: BigInt): SInt = Lit(value)
-  /** Create an SInt literal with fixed width. */
-  def apply(value: BigInt, width: Int): SInt = Lit(value, width)
-
-  /** Create an SInt literal with specified width. */
-  def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
   /** Create a SInt with the specified range */
   def apply(range: Range): SInt = {
-    width(range.getWidth)
+    apply(range.getWidth)
   }
   /** Create a SInt with the specified range */
   def apply(range: (NumericBound[Int], NumericBound[Int])): SInt = {
     apply(KnownSIntRange(range._1, range._2))
   }
 
-  def Lit(value: BigInt): SInt = Lit(value, Width())
-  def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
    /** Create an SInt literal with specified width. */
-  def Lit(value: BigInt, width: Width): SInt = {
+  protected def Lit(value: BigInt, width: Width): SInt = {
 
     val lit = SLit(value, width)
     val result = new SInt(lit.width, Some(lit))
@@ -697,20 +683,6 @@ object SInt {
     result.binding = LitBinding()
     result
   }
-  /** Create a SInt with a specified width - compatibility with Chisel2. */
-  def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
-  /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
-  /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
-  def apply(dir: Direction): SInt = apply(dir, Width())
-  def apply(dir: Direction, wWidth: Width): SInt = {
-    val result = apply(wWidth)
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
 }
 
 // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ac0caa45..69d02f9c 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -4,6 +4,8 @@
 // moving to the more standard package naming convention chisel3 (lowercase c).
 
 package object Chisel {     // scalastyle:ignore package.object.name
+  import chisel3.internal.firrtl.Width
+
   implicit val defaultCompileOptions = chisel3.core.ExplicitCompileOptions.NotStrict
   type Direction = chisel3.core.Direction
 
@@ -40,8 +42,6 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val stop = chisel3.core.stop
 
   trait UIntFactory extends chisel3.core.UIntFactory {
-    import chisel3.internal.firrtl.Width
-
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
@@ -80,6 +80,39 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): UInt = apply(width)
   }
 
+  trait SIntFactory extends chisel3.core.SIntFactory {
+    /** Create a SInt type or port with fixed width. */
+    def width(width: Int): SInt = apply(Width(width))
+    /** Create an SInt type with specified width. */
+    def width(width: Width): SInt = apply(width)
+
+    /** Create an SInt literal with inferred width. */
+    def apply(value: BigInt): SInt = Lit(value)
+    /** Create an SInt literal with fixed width. */
+    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+
+    /** Create an SInt literal with specified width. */
+    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+    def Lit(value: BigInt): SInt = Lit(value, Width())
+    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+
+    /** Create a SInt with a specified width - compatibility with Chisel2. */
+    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+    /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
+    /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
+    def apply(dir: Direction): SInt = apply(dir, Width())
+    def apply(dir: Direction, wWidth: Width): SInt = {
+      val result = apply(wWidth)
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
   object Bits extends UIntFactory
@@ -87,7 +120,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type UInt = chisel3.core.UInt
   object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
-  val SInt = chisel3.core.SInt
+  object SInt extends SIntFactory
   type Bool = chisel3.core.Bool
   val Bool = chisel3.core.Bool
   val Mux = chisel3.core.Mux
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 84a4779e..1161a1ca 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -38,20 +38,20 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use n.U(width.W)")
     def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         Width(width))
 
     /** Create a UInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width)")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use value.U(width.W)")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
@@ -59,20 +59,46 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def apply(value: BigInt): UInt = apply(value, Width())
 
     /** Create a UInt with a specified width */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
     def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width: Width)")
+    @deprecated("chisel3, will be removed by end of 2016, use UInt(width)")
     def width(width: Width): UInt = apply(width)
   }
 
+  trait SIntFactory extends chisel3.core.SIntFactory {
+    /** Create a SInt type or port with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use SInt(width.W)")
+    def width(width: Int): SInt = apply(Width(width))
+    /** Create an SInt type with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use SInt(width)")
+    def width(width: Width): SInt = apply(width)
+
+    /** Create an SInt literal with inferred width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    def apply(value: BigInt): SInt = Lit(value)
+    /** Create an SInt literal with fixed width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width.W)")
+    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+
+    /** Create an SInt literal with specified width. */
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+
+    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    def Lit(value: BigInt): SInt = Lit(value, Width())
+
+    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+  }
+
   object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
   object UInt extends UIntFactory
   type SInt = chisel3.core.SInt
-  val SInt = chisel3.core.SInt
+  object SInt extends SIntFactory
   type FixedPoint = chisel3.core.FixedPoint
   val FixedPoint = chisel3.core.FixedPoint
   type Bool = chisel3.core.Bool
-- 
cgit v1.2.3


From b0cc0c93a80aec5bed54cfb11923636c09b7e180 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:21:59 -0800
Subject: SInt conversion finished, everything builds again

---
 build.sbt                                          |  5 +-
 .../src/main/scala/chisel3/core/Bits.scala         | 17 +++---
 .../src/main/scala/chisel3/core/package.scala      | 65 ++++++++++++++++++----
 src/main/scala/chisel3/compatibility.scala         |  1 +
 src/main/scala/chisel3/package.scala               |  2 +-
 src/test/scala/chiselTests/AnnotatingExample.scala | 22 ++++----
 src/test/scala/chiselTests/DriverSpec.scala        |  4 +-
 7 files changed, 81 insertions(+), 35 deletions(-)

diff --git a/build.sbt b/build.sbt
index 4ad1cf77..dd36f25f 100644
--- a/build.sbt
+++ b/build.sbt
@@ -18,7 +18,8 @@ lazy val commonSettings = Seq (
   version := "3.1-SNAPSHOT",
   git.remoteRepo := "git@github.com:ucb-bar/chisel3.git",
   autoAPIMappings := true,
-  scalaVersion := "2.11.7"
+  scalaVersion := "2.11.7",
+  scalacOptions := Seq("-deprecation")
 )
 
 val defaultVersions = Map("firrtl" -> "1.1-SNAPSHOT")
@@ -82,7 +83,7 @@ lazy val chiselSettings = Seq (
         "edu.berkeley.cs" %% dep % sys.props.getOrElse(dep + "Version", defaultVersions(dep))
     }
   },
-  
+
   // Tests from other projects may still run concurrently.
   parallelExecution in Test := true,
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 7e467b88..aa73abf5 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -134,7 +134,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
     }
     val w = x - y + 1
     if (isLit()) {
-      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w)
+      ((litValue >> y) & ((BigInt(1) << w) - 1)).asUInt(w.W)
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, UInt(Width(w)), BitsExtractOp, this.ref, ILit(x), ILit(y)))
@@ -403,7 +403,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   private[chisel3] def toType = s"UInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asUInt(width).asInstanceOf[this.type]
+    value.asUInt(width.W).asInstanceOf[this.type]
 
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
@@ -563,13 +563,13 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
   private[chisel3] def toType = s"SInt$width"
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    SInt(value, width).asInstanceOf[this.type]
+    value.asSInt(width.W).asInstanceOf[this.type]
 
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
   final def unary_-% (): SInt = macro SourceInfoTransform.noArg
 
-  def unary_- (implicit sourceInfo: SourceInfo): SInt = SInt(0) - this
-  def unary_-% (implicit sourceInfo: SourceInfo): SInt = SInt(0) -% this
+  def unary_- (implicit sourceInfo: SourceInfo): SInt = 0.S - this
+  def unary_-% (implicit sourceInfo: SourceInfo): SInt = 0.S -% this
 
   /** add (default - no growth) operator */
   override def do_+ (that: SInt)(implicit sourceInfo: SourceInfo): SInt =
@@ -637,7 +637,7 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
 
   final def abs(): UInt = macro SourceInfoTransform.noArg
 
-  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < SInt(0), (-this).asUInt, this.asUInt)
+  def do_abs(implicit sourceInfo: SourceInfo): UInt = Mux(this < 0.S, (-this).asUInt, this.asUInt)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): SInt =
     binop(sourceInfo, SInt(this.width + that), ShiftLeftOp, that)
@@ -675,8 +675,7 @@ trait SIntFactory {
   }
 
    /** Create an SInt literal with specified width. */
-  protected def Lit(value: BigInt, width: Width): SInt = {
-
+  protected[chisel3] def Lit(value: BigInt, width: Width): SInt = {
     val lit = SLit(value, width)
     val result = new SInt(lit.width, Some(lit))
     // Bind result to being an Literal
@@ -685,6 +684,8 @@ trait SIntFactory {
   }
 }
 
+object SInt extends SIntFactory
+
 // REVIEW TODO: Why does this extend UInt and not Bits? Does defining airth
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 554e6238..7fb05c75 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -18,23 +18,62 @@ package chisel3 {
     * Prefer storing the result and then extracting from it.
     */
     implicit class fromIntToLiteral(val x: Int) {
-      def U: UInt = UInt.Lit(BigInt(x), Width())    // scalastyle:ignore method.name
-      def S: SInt = SInt(BigInt(x), Width())    // scalastyle:ignore method.name
+      /** Int to UInt conversion, recommended style for constants.
+        */
+      def U: UInt = UInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      /** Int to SInt conversion, recommended style for constants.
+        */
+      def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
 
+      /** Int to UInt conversion, recommended style for variables.
+        */
       def asUInt(): UInt = UInt.Lit(x, Width())
-      def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      def asSInt(width: Int): SInt = SInt(x, Width(width))
+      /** Int to SInt conversion, recommended style for variables.
+        */
+      def asSInt(): SInt = SInt.Lit(x, Width())
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      //def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      //def asSInt(width: Int): SInt = SInt(x, Width(width))
+
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
-      def U: UInt = UInt.Lit(x, Width())       // scalastyle:ignore method.name
-      def S: SInt = SInt(x, Width())       // scalastyle:ignore method.name
+      /** Int to UInt conversion, recommended style for constants.
+        */
+      def U: UInt = UInt.Lit(x, Width())  // scalastyle:ignore method.name
+      /** Int to SInt conversion, recommended style for constants.
+        */
+      def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
 
+      /** Int to UInt conversion, recommended style for variables.
+        */
       def asUInt(): UInt = UInt.Lit(x, Width())
-      def asSInt(): SInt = SInt(x, Width())
-      def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      def asSInt(width: Int): SInt = SInt(x, width)
+      /** Int to SInt conversion, recommended style for variables.
+        */
+      def asSInt(): SInt = SInt.Lit(x, Width())
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+
+      /** Int to UInt conversion with specified width, recommended style for variables.
+        */
+      // def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
+      /** Int to SInt conversion with specified width, recommended style for variables.
+        */
+      // def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
@@ -65,11 +104,15 @@ package chisel3 {
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
-      def B: Bool = Bool(x)       // scalastyle:ignore method.name
+      def B: Bool = Bool(x)  // scalastyle:ignore method.name
     }
 
     implicit class fromDoubleToLiteral(val x: Double) {
       def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
     }
+
+    implicit class fromIntToWidth(val x: Int) {
+      def W: Width = Width(x)  // scalastyle:ignore method.name
+    }
   }
 }
\ No newline at end of file
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 69d02f9c..a9365ac3 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -147,6 +147,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 1161a1ca..1a100480 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -180,7 +180,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
   implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
   implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
-
+  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
diff --git a/src/test/scala/chiselTests/AnnotatingExample.scala b/src/test/scala/chiselTests/AnnotatingExample.scala
index 04228d6b..0be3ba59 100644
--- a/src/test/scala/chiselTests/AnnotatingExample.scala
+++ b/src/test/scala/chiselTests/AnnotatingExample.scala
@@ -24,8 +24,8 @@ import scala.util.DynamicVariable
 
 class SomeSubMod(param1: Int, param2: Int) extends Module {
   val io = new Bundle {
-    val in = UInt(INPUT, 16)
-    val out = SInt(OUTPUT, 32)
+    val in = Input(UInt(16.W))
+    val out = Output(SInt(32.W))
   }
   val annotate = MyBuilder.myDynamicContext.annotationMap
 
@@ -36,18 +36,18 @@ class SomeSubMod(param1: Int, param2: Int) extends Module {
 
 class AnnotatingExample extends Module {
   val io = new Bundle {
-    val a  = UInt(INPUT, 32)
-    val b  = UInt(INPUT, 32)
-    val e  = Bool(INPUT)
-    val z  = UInt(OUTPUT, 32)
-    val v  = Bool(OUTPUT)
+    val a  = Input(UInt(32.W))
+    val b  = Input(UInt(32.W))
+    val e  = Input(Bool())
+    val z  = Output(UInt(32.W))
+    val v  = Output(Bool())
     val bun = new Bundle {
-      val nested_1 = UInt(INPUT, 12)
-      val nested_2 = Bool(OUTPUT)
+      val nested_1 = Input(UInt(12.W))
+      val nested_2 = Output(Bool())
     }
   }
-  val x = Reg(UInt(width = 32))
-  val y = Reg(UInt(width = 32))
+  val x = Reg(UInt(32.W))
+  val y = Reg(UInt(32.W))
 
   val subModule1 = Module(new SomeSubMod(1, 2))
   val subModule2 = Module(new SomeSubMod(3, 4))
diff --git a/src/test/scala/chiselTests/DriverSpec.scala b/src/test/scala/chiselTests/DriverSpec.scala
index 4f9619e3..d77dbaf1 100644
--- a/src/test/scala/chiselTests/DriverSpec.scala
+++ b/src/test/scala/chiselTests/DriverSpec.scala
@@ -8,8 +8,8 @@ import org.scalatest.{Matchers, FreeSpec}
 
 class DummyModule extends Module {
   val io = IO(new Bundle {
-    val in = UInt(INPUT, 1)
-    val out = UInt(OUTPUT, 1)
+    val in = Input(UInt(1.W))
+    val out = Output(UInt(1.W))
   })
   io.out := io.in
 }
-- 
cgit v1.2.3


From cd904da0aa0e96ba679906a3ee5dbdc068eace48 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 11:33:20 -0800
Subject: Restyle Bool constructors, move compatibility deprecations into
 compatibility package object

---
 .../src/main/scala/chisel3/core/Aggregate.scala    |  4 +-
 .../src/main/scala/chisel3/core/Bits.scala         | 20 +++------
 .../src/main/scala/chisel3/core/package.scala      |  8 +++-
 src/main/scala/chisel3/compatibility.scala         | 48 ++++++++++++++++++++--
 src/main/scala/chisel3/compatibility/Main.scala    | 19 ---------
 src/main/scala/chisel3/compatibility/debug.scala   | 10 -----
 .../chisel3/compatibility/throwException.scala     | 14 -------
 src/main/scala/chisel3/package.scala               |  9 +++-
 8 files changed, 67 insertions(+), 65 deletions(-)
 delete mode 100644 src/main/scala/chisel3/compatibility/Main.scala
 delete mode 100644 src/main/scala/chisel3/compatibility/debug.scala
 delete mode 100644 src/main/scala/chisel3/compatibility/throwException.scala

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 77a1b57a..8fdcb260 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -261,14 +261,14 @@ trait VecLike[T <: Data] extends collection.IndexedSeq[T] with HasId {
   def forall(p: T => Bool): Bool = macro SourceInfoTransform.pArg
 
   def do_forall(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
-    (this map p).fold(Bool(true))(_ && _)
+    (this map p).fold(true.B)(_ && _)
 
   /** Outputs true if p outputs true for at least one element.
     */
   def exists(p: T => Bool): Bool = macro SourceInfoTransform.pArg
 
   def do_exists(p: T => Bool)(implicit sourceInfo: SourceInfo): Bool =
-    (this map p).fold(Bool(false))(_ || _)
+    (this map p).fold(false.B)(_ || _)
 
   /** Outputs true if the vector contains at least one element equal to x (using
     * the === operator).
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index aa73abf5..b81679b6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -92,7 +92,7 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
       Builder.error(s"Negative bit indices are illegal (got $x)")
     }
     if (isLit()) {
-      Bool(((litValue() >> x.toInt) & 1) == 1)
+      (((litValue() >> x.toInt) & 1) == 1).asBool
     } else {
       Binding.checkSynthesizable(this, s"'this' ($this)")
       pushOp(DefPrim(sourceInfo, Bool(), BitsExtractOp, this.ref, ILit(x), ILit(x)))
@@ -698,7 +698,7 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
 
   override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
     require((value == 0 || value == 1) && width == 1)
-    Bool(value == 1).asInstanceOf[this.type]
+    (value == 1).asBool.asInstanceOf[this.type]
   }
 
   // REVIEW TODO: Why does this need to exist and have different conventions
@@ -736,31 +736,23 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
   def do_asClock(implicit sourceInfo: SourceInfo): Clock = pushOp(DefPrim(sourceInfo, Clock(), AsClockOp, ref))
 }
 
-object Bool {
+trait BoolFactory {
   /** Creates an empty Bool.
    */
   def apply(): Bool = new Bool()
 
   /** Creates Bool literal.
    */
-  def apply(x: Boolean): Bool = Lit(x)
-  def Lit(x: Boolean): Bool = {
+  protected[chisel3] def Lit(x: Boolean): Bool = {
     val result = new Bool(Some(ULit(if (x) 1 else 0, Width(1))))
     // Bind result to being an Literal
     result.binding = LitBinding()
     result
   }
-  /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-  def apply(dir: Direction): Bool = {
-    val result = apply()
-    dir match {
-      case Direction.Input => Input(result)
-      case Direction.Output => Output(result)
-      case Direction.Unspecified => result
-    }
-  }
 }
 
+object Bool extends BoolFactory
+
 object Mux {
   /** Creates a mux, whose output is one of the inputs depending on the
     * value of the condition.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 7fb05c75..ac10a140 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -104,7 +104,13 @@ package chisel3 {
     }
 
     implicit class fromBooleanToLiteral(val x: Boolean) {
-      def B: Bool = Bool(x)  // scalastyle:ignore method.name
+      /** Boolean to Bool conversion, recommended style for constants.
+        */
+      def B: Bool = Bool.Lit(x)  // scalastyle:ignore method.name
+
+      /** Boolean to Bool conversion, recommended style for variables.
+        */
+      def asBool: Bool = Bool.Lit(x)
     }
 
     implicit class fromDoubleToLiteral(val x: Double) {
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index a9365ac3..9d0e266b 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -113,6 +113,22 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
   }
 
+  trait BoolFactory extends chisel3.core.BoolFactory {
+    /** Creates Bool literal.
+     */
+    def apply(x: Boolean): Bool = Lit(x)
+
+    /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
+    def apply(dir: Direction): Bool = {
+      val result = apply()
+      dir match {
+        case chisel3.core.Direction.Input => chisel3.core.Input(result)
+        case chisel3.core.Direction.Output => chisel3.core.Output(result)
+        case chisel3.core.Direction.Unspecified => result
+      }
+    }
+  }
+
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
   object Bits extends UIntFactory
@@ -122,7 +138,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type SInt = chisel3.core.SInt
   object SInt extends SIntFactory
   type Bool = chisel3.core.Bool
-  val Bool = chisel3.core.Bool
+  object Bool extends BoolFactory
   val Mux = chisel3.core.Mux
 
   type BlackBox = chisel3.core.BlackBox
@@ -152,9 +168,33 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
   val ImplicitConversions = chisel3.util.ImplicitConversions
-  val chiselMain = chisel3.compatibility.chiselMain
-  val throwException = chisel3.compatibility.throwException
-  val debug = chisel3.compatibility.debug
+
+  object chiselMain {
+    import java.io.File
+
+    def apply[T <: Module](args: Array[String], gen: () => T): Unit =
+      Predef.assert(false, "No more chiselMain in Chisel3")
+
+    def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
+      val circuit = Driver.elaborate(gen)
+      Driver.parseArgs(args)
+      val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+      Driver.dumpFirrtl(circuit, Option(output_file))
+    }
+  }
+
+  @deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
+  object debug {  // scalastyle:ignore object.name
+    def apply (arg: Data): Data = arg
+  }
+
+  @throws(classOf[Exception])
+  object throwException {
+    def apply(s: String, t: Throwable = null) = {
+      val xcpt = new Exception(s, t)
+      throw xcpt
+    }
+  }
 
   object testers {    // scalastyle:ignore object.name
     type BasicTester = chisel3.testers.BasicTester
diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
deleted file mode 100644
index a41599a3..00000000
--- a/src/main/scala/chisel3/compatibility/Main.scala
+++ /dev/null
@@ -1,19 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import java.io.File
-
-import chisel3._
-
-@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
-  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
-    Predef.assert(false, "No more chiselMain in Chisel3")
-
-  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
-    val circuit = Driver.elaborate(gen)
-    Driver.parseArgs(args)
-    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
-    Driver.dumpFirrtl(circuit, Option(output_file))
-  }
-}
diff --git a/src/main/scala/chisel3/compatibility/debug.scala b/src/main/scala/chisel3/compatibility/debug.scala
deleted file mode 100644
index d9f6e4b0..00000000
--- a/src/main/scala/chisel3/compatibility/debug.scala
+++ /dev/null
@@ -1,10 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import chisel3.core._
-
-@deprecated("debug doesn't do anything in Chisel3 as no pruning happens in the frontend", "chisel3")
-object debug {  // scalastyle:ignore object.name
-  def apply (arg: Data): Data = arg
-}
diff --git a/src/main/scala/chisel3/compatibility/throwException.scala b/src/main/scala/chisel3/compatibility/throwException.scala
deleted file mode 100644
index 3e8b33e6..00000000
--- a/src/main/scala/chisel3/compatibility/throwException.scala
+++ /dev/null
@@ -1,14 +0,0 @@
-// See LICENSE for license details.
-
-package chisel3.compatibility
-
-import chisel3._
-
-@deprecated("throwException doesn't exist in Chisel3", "3.0.0")
-@throws(classOf[Exception])
-object throwException {
-  def apply(s: String, t: Throwable = null) = {
-    val xcpt = new Exception(s, t)
-    throw xcpt
-  }
-}
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 1a100480..8ac76867 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -93,6 +93,13 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
   }
 
+  trait BoolFactory extends chisel3.core.BoolFactory {
+    /** Creates Bool literal.
+     */
+    @deprecated("chisel3, will be removed by end of 2016, use x.B")
+    def apply(x: Boolean): Bool = Lit(x)
+  }
+
   object Bits extends UIntFactory
   type Num[T <: Data] = chisel3.core.Num[T]
   type UInt = chisel3.core.UInt
@@ -102,7 +109,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type FixedPoint = chisel3.core.FixedPoint
   val FixedPoint = chisel3.core.FixedPoint
   type Bool = chisel3.core.Bool
-  val Bool = chisel3.core.Bool
+  object Bool extends BoolFactory
   val Mux = chisel3.core.Mux
 
   type BlackBox = chisel3.core.BlackBox
-- 
cgit v1.2.3


From 54d3f8dc054e55dfbd01d1aa034169a3dabe89f2 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:01:03 -0800
Subject: Restyle a lot of test code, mainly with regex

---
 .../src/main/scala/chisel3/core/Bits.scala         |  4 +-
 .../src/main/scala/chisel3/core/SeqUtils.scala     |  2 +-
 .../src/main/scala/chisel3/core/When.scala         |  4 +-
 .../src/main/scala/chisel3/core/package.scala      | 18 ++++++++
 src/main/scala/chisel3/compatibility.scala         |  6 +++
 src/main/scala/chisel3/package.scala               | 50 ++++++++++++++-------
 src/main/scala/chisel3/util/Arbiter.scala          | 28 ++++++------
 src/main/scala/chisel3/util/BitPat.scala           |  2 +-
 src/main/scala/chisel3/util/Bitwise.scala          |  6 +--
 src/main/scala/chisel3/util/CircuitMath.scala      |  8 ++--
 src/main/scala/chisel3/util/Counter.scala          | 14 +++---
 src/main/scala/chisel3/util/Decoupled.scala        | 24 +++++-----
 .../scala/chisel3/util/ImplicitConversions.scala   |  4 +-
 src/main/scala/chisel3/util/LFSR.scala             |  4 +-
 src/main/scala/chisel3/util/OneHot.scala           | 10 ++---
 src/main/scala/chisel3/util/Reg.scala              |  2 +-
 src/main/scala/chisel3/util/Valid.scala            |  2 +-
 src/test/scala/chiselTests/Assert.scala            |  8 ++--
 src/test/scala/chiselTests/BetterNamingTests.scala |  4 +-
 src/test/scala/chiselTests/BlackBox.scala          | 46 +++++++++----------
 src/test/scala/chiselTests/BundleWire.scala        | 20 ++++-----
 src/test/scala/chiselTests/Clock.scala             |  2 +-
 .../scala/chiselTests/CompileOptionsTest.scala     | 52 +++++++++++-----------
 src/test/scala/chiselTests/ComplexAssign.scala     | 20 ++++-----
 src/test/scala/chiselTests/Counter.scala           |  8 ++--
 src/test/scala/chiselTests/Decoder.scala           |  8 ++--
 src/test/scala/chiselTests/Direction.scala         |  8 ++--
 .../scala/chiselTests/EnableShiftRegister.scala    | 12 ++---
 src/test/scala/chiselTests/GCD.scala               | 12 ++---
 src/test/scala/chiselTests/IOCompatibility.scala   | 10 ++---
 src/test/scala/chiselTests/LFSR16.scala            |  4 +-
 src/test/scala/chiselTests/MemorySearch.scala      | 14 +++---
 src/test/scala/chiselTests/Module.scala            |  8 ++--
 .../chiselTests/ModuleExplicitResetSpec.scala      | 10 ++---
 src/test/scala/chiselTests/MulLookup.scala         |  8 ++--
 src/test/scala/chiselTests/MultiAssign.scala       |  4 +-
 src/test/scala/chiselTests/OptionBundle.scala      |  8 ++--
 src/test/scala/chiselTests/Padding.scala           |  6 +--
 .../scala/chiselTests/ParameterizedModule.scala    |  8 ++--
 src/test/scala/chiselTests/PrintableSpec.scala     | 26 +++++------
 src/test/scala/chiselTests/Printf.scala            |  6 +--
 src/test/scala/chiselTests/Reg.scala               | 10 ++---
 src/test/scala/chiselTests/Risc.scala              | 22 ++++-----
 src/test/scala/chiselTests/SIntOps.scala           | 26 +++++------
 src/test/scala/chiselTests/Stack.scala             | 20 ++++-----
 src/test/scala/chiselTests/Tbl.scala               | 20 ++++-----
 src/test/scala/chiselTests/TesterDriverSpec.scala  |  4 +-
 src/test/scala/chiselTests/UIntOps.scala           | 26 +++++------
 src/test/scala/chiselTests/Vec.scala               |  8 ++--
 src/test/scala/chiselTests/VectorPacketIO.scala    |  2 +-
 src/test/scala/chiselTests/VendingMachine.scala    |  2 +-
 src/test/scala/chiselTests/When.scala              | 48 ++++++++++----------
 src/test/scala/cookbook/Bundle2UInt.scala          | 10 ++---
 src/test/scala/cookbook/CookbookSpec.scala         |  2 +-
 src/test/scala/cookbook/UInt2Bundle.scala          | 10 ++---
 src/test/scala/cookbook/UInt2VecOfBool.scala       | 10 ++---
 src/test/scala/cookbook/VecOfBool2UInt.scala       |  4 +-
 57 files changed, 383 insertions(+), 341 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index b81679b6..354512e1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -690,7 +690,7 @@ object SInt extends SIntFactory
 // operations on a Bool make sense?
 /** A data type for booleans, defined as a single bit indicating true or false.
   */
-sealed class Bool(lit: Option[ULit] = None) extends UInt(Width(1), lit) {
+sealed class Bool(lit: Option[ULit] = None) extends UInt(1.W, lit) {
   private[core] override def cloneTypeWidth(w: Width): this.type = {
     require(!w.known || w.get == 1)
     new Bool().asInstanceOf[this.type]
@@ -762,7 +762,7 @@ object Mux {
     * @param alt the value chosen when `cond` is false
     * @example
     * {{{
-    * val muxOut = Mux(data_in === UInt(3), UInt(3, 4), UInt(0, 4))
+    * val muxOut = Mux(data_in === 3.U, 3.U(4.W), 0.U(4.W))
     * }}}
     */
   def apply[T <: Data](cond: Bool, con: T, alt: T): T = macro MuxTransform.apply[T]
diff --git a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
index da4f2d94..e435860e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/SeqUtils.scala
@@ -25,7 +25,7 @@ private[chisel3] object SeqUtils {
     }
   }
 
-  /** Outputs the number of elements that === Bool(true).
+  /** Outputs the number of elements that === true.B.
     */
   def count(in: Seq[Bool]): UInt = macro SourceInfoTransform.inArg
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/When.scala b/chiselFrontend/src/main/scala/chisel3/core/When.scala
index 196e7903..7501ebb1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/When.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/When.scala
@@ -18,9 +18,9 @@ object when {  // scalastyle:ignore object.name
     *
     * @example
     * {{{
-    * when ( myData === UInt(3) ) {
+    * when ( myData === 3.U ) {
     *   // Some logic to run when myData equals 3.
-    * } .elsewhen ( myData === UInt(1) ) {
+    * } .elsewhen ( myData === 1.U ) {
     *   // Some logic to run when myData equals 1.
     * } .otherwise {
     *   // Some logic to run when myData is neither 3 nor 1.
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index ac10a140..cae64df6 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -24,6 +24,12 @@ package chisel3 {
       /** Int to SInt conversion, recommended style for constants.
         */
       def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      /** Int to UInt conversion with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      /** Int to SInt conversion with specified width, recommended style for constants.
+        */
+      def S(width: Width): SInt = SInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
@@ -54,6 +60,12 @@ package chisel3 {
       /** Int to SInt conversion, recommended style for constants.
         */
       def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
+      /** Int to UInt conversion with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(x, width)  // scalastyle:ignore method.name
+      /** Int to SInt conversion with specified width, recommended style for constants.
+        */
+      def S(width: Width): SInt = SInt.Lit(x, width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
@@ -77,7 +89,13 @@ package chisel3 {
     }
 
     implicit class fromStringToLiteral(val x: String) {
+      /** String to UInt parse, recommended style for constants.
+        */
       def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+
+      /** String to UInt parse, recommended style for variables.
+        */
+      def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
     }
 
     object fromStringToLiteral {
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 9d0e266b..625628dd 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -41,6 +41,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val assert = chisel3.core.assert
   val stop = chisel3.core.stop
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
@@ -80,6 +82,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
     def width(width: Int): SInt = apply(Width(width))
@@ -113,6 +117,8 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 8ac76867..8b5b8a46 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,71 +32,89 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    *
+    * Some recommended regex replacements:
+    * (note: these are not guaranteed to handle all edge cases! check all replacements!)
+    * Bool((true|false)) => $1.B
+    * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
+    * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
+    * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
+    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width)?\s*=\s*(\d+)\) => $1.U($2.W)
+    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U")
+    @deprecated("use n.U", "chisel3, will be removed by end of 2016")
     def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         chisel3.core.fromStringToLiteral.parsedWidth(n))
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use n.U(width.W)")
+    @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
         Width(width))
 
     /** Create a UInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width)")
+    @deprecated("use value.U(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): UInt = Lit(value, width)
 
     /** Create a UInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U(width.W)")
+    @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.U")
+    @deprecated("use value.U", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): UInt = apply(value, Width())
 
     /** Create a UInt with a specified width */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width.W)")
+    @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): UInt = apply(Width(width))
 
     /** Create a UInt port with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use UInt(width)")
+    @deprecated("use UInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): UInt = apply(width)
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width.W)")
+    @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2016")
     def width(width: Int): SInt = apply(Width(width))
     /** Create an SInt type with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use SInt(width)")
+    @deprecated("use SInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt): SInt = Lit(value)
     /** Create an SInt literal with fixed width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width.W)")
+    @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Int): SInt = Lit(value, width)
 
     /** Create an SInt literal with specified width. */
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def apply(value: BigInt, width: Width): SInt = Lit(value, width)
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S")
+    @deprecated("use value.S", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt): SInt = Lit(value, Width())
 
-    @deprecated("chisel3, will be removed by end of 2016, use value.S(width)")
+    @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
     def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
   }
 
+  /** This contains literal constructor factory methods that are deprecated as of Chisel3.
+    * These will be removed very soon. It's recommended you move your code soon.
+    */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
-    @deprecated("chisel3, will be removed by end of 2016, use x.B")
+    @deprecated("use x.B", "chisel3, will be removed by end of 2016")
     def apply(x: Boolean): Bool = Lit(x)
   }
 
diff --git a/src/main/scala/chisel3/util/Arbiter.scala b/src/main/scala/chisel3/util/Arbiter.scala
index 89bb644a..d755b620 100644
--- a/src/main/scala/chisel3/util/Arbiter.scala
+++ b/src/main/scala/chisel3/util/Arbiter.scala
@@ -18,7 +18,7 @@ import chisel3.core.ExplicitCompileOptions.NotStrict
 class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
   val in  = Flipped(Vec(n, Decoupled(gen)))
   val out = Decoupled(gen)
-  val chosen = Output(UInt.width(log2Up(n)))
+  val chosen = Output(UInt(log2Up(n).W))
 }
 
 /** Arbiter Control determining which producer has access
@@ -26,8 +26,8 @@ class ArbiterIO[T <: Data](gen: T, n: Int) extends Bundle {
 private object ArbiterCtrl {
   def apply(request: Seq[Bool]): Seq[Bool] = request.length match {
     case 0 => Seq()
-    case 1 => Seq(Bool(true))
-    case _ => Bool(true) +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
+    case 1 => Seq(true.B)
+    case _ => true.B +: request.tail.init.scanLeft(request.head)(_ || _).map(!_)
   }
 }
 
@@ -43,8 +43,8 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
   if (count > 1) {
     val lockCount = Counter(count)
     val lockIdx = Reg(UInt())
-    val locked = lockCount.value =/= UInt(0)
-    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(Bool(true))
+    val locked = lockCount.value =/= 0.U
+    val wantsLock = needsLock.map(_(io.out.bits)).getOrElse(true.B)
 
     when (io.out.fire() && wantsLock) {
       lockIdx := io.chosen
@@ -53,7 +53,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 
     when (locked) { io.chosen := lockIdx }
     for ((in, (g, i)) <- io.in zip grant.zipWithIndex)
-      in.ready := Mux(locked, lockIdx === UInt(i), g) && io.out.ready
+      in.ready := Mux(locked, lockIdx === i.asUInt, g) && io.out.ready
   } else {
     for ((in, g) <- io.in zip grant)
       in.ready := g && io.out.ready
@@ -63,7 +63,7 @@ abstract class LockingArbiterLike[T <: Data](gen: T, n: Int, count: Int, needsLo
 class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   lazy val lastGrant = RegEnable(io.chosen, io.out.fire())
-  lazy val grantMask = (0 until n).map(UInt(_) > lastGrant)
+  lazy val grantMask = (0 until n).map(_.asUInt > lastGrant)
   lazy val validMask = io.in zip grantMask map { case (in, g) => in.valid && g }
 
   override def grant: Seq[Bool] = {
@@ -71,20 +71,20 @@ class LockingRRArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[
     (0 until n).map(i => ctrl(i) && grantMask(i) || ctrl(i + n))
   }
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
   for (i <- n-1 to 1 by -1)
-    when (validMask(i)) { choice := UInt(i) }
+    when (validMask(i)) { choice := i.asUInt }
 }
 
 class LockingArbiter[T <: Data](gen: T, n: Int, count: Int, needsLock: Option[T => Bool] = None)
     extends LockingArbiterLike[T](gen, n, count, needsLock) {
   def grant: Seq[Bool] = ArbiterCtrl(io.in.map(_.valid))
 
-  override lazy val choice = Wire(init=UInt(n-1))
+  override lazy val choice = Wire(init=(n-1).asUInt)
   for (i <- n-2 to 0 by -1)
-    when (io.in(i).valid) { choice := UInt(i) }
+    when (io.in(i).valid) { choice := i.asUInt }
 }
 
 /** Hardware module that is used to sequence n producers into 1 consumer.
@@ -112,11 +112,11 @@ class RRArbiter[T <: Data](gen:T, n: Int) extends LockingRRArbiter[T](gen, n, 1)
 class Arbiter[T <: Data](gen: T, n: Int) extends Module {
   val io = IO(new ArbiterIO(gen, n))
 
-  io.chosen := UInt(n-1)
+  io.chosen := (n-1).asUInt
   io.out.bits := io.in(n-1).bits
   for (i <- n-2 to 0 by -1) {
     when (io.in(i).valid) {
-      io.chosen := UInt(i)
+      io.chosen := i.asUInt
       io.out.bits := io.in(i).bits
     }
   }
diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala
index e58258c7..9c9909cd 100644
--- a/src/main/scala/chisel3/util/BitPat.scala
+++ b/src/main/scala/chisel3/util/BitPat.scala
@@ -57,7 +57,7 @@ object BitPat {
     */
   def bitPatToUInt(x: BitPat): UInt = {
     require(x.mask == (BigInt(1) << x.getWidth) - 1)
-    UInt(x.value, x.getWidth)
+    x.value.asUInt(x.getWidth.W)
   }
 
   /** Allows UInts to be used where a BitPat is expected, useful for when an
diff --git a/src/main/scala/chisel3/util/Bitwise.scala b/src/main/scala/chisel3/util/Bitwise.scala
index 289d27b1..22326972 100644
--- a/src/main/scala/chisel3/util/Bitwise.scala
+++ b/src/main/scala/chisel3/util/Bitwise.scala
@@ -38,10 +38,10 @@ object Fill {
     */
   def apply(n: Int, x: UInt): UInt = {
     n match {
-      case 0 => UInt.width(0)
+      case 0 => UInt(0.W)
       case 1 => x
       case _ if x.isWidthKnown && x.getWidth == 1 =>
-        Mux(x.toBool, UInt((BigInt(1) << n) - 1, n), UInt(0, n))
+        Mux(x.toBool, ((BigInt(1) << n) - 1).asUInt(n.W), 0.U(n.W))
       case _ if n > 1 =>
         val p2 = Array.ofDim[UInt](log2Up(n + 1))
         p2(0) = x
@@ -61,7 +61,7 @@ object Reverse {
       // This esoterica improves simulation performance
       var res = in
       var shift = length >> 1
-      var mask = UInt((BigInt(1) << length) - 1, length)
+      var mask = ((BigInt(1) << length) - 1).asUInt(length.W)
       do {
         mask = mask ^ (mask(length-shift-1,0) << shift)
         res = ((res >> shift) & mask) | ((res(length-shift-1,0) << shift) & ~mask)
diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index d478e10e..83e5feb1 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -10,15 +10,15 @@ import chisel3._
 object Log2 {
   /** Returns the base-2 integer logarithm of the least-significant `width` bits of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits, width: Int): UInt = {
     if (width < 2) {
-      UInt(0)
+      0.U
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt(width-1), apply(x, width-1))
+      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
@@ -30,7 +30,7 @@ object Log2 {
 
   /** Returns the base-2 integer logarithm of an UInt.
     *
-    * @note The result is truncated, so e.g. Log2(UInt(13)) === UInt(3)
+    * @note The result is truncated, so e.g. Log2(13.U) === 3.U
     */
   def apply(x: Bits): UInt = apply(x, x.getWidth)
 
diff --git a/src/main/scala/chisel3/util/Counter.scala b/src/main/scala/chisel3/util/Counter.scala
index ba66d667..6d59eaaf 100644
--- a/src/main/scala/chisel3/util/Counter.scala
+++ b/src/main/scala/chisel3/util/Counter.scala
@@ -12,7 +12,7 @@ import chisel3._
   */
 class Counter(val n: Int) {
   require(n >= 0)
-  val value = if (n > 1) Reg(init=UInt(0, log2Up(n))) else UInt(0)
+  val value = if (n > 1) Reg(init=0.U(log2Up(n).W)) else 0.U
 
   /** Increment the counter, returning whether the counter currently is at the
     * maximum and will wrap. The incremented value is registered and will be
@@ -20,14 +20,14 @@ class Counter(val n: Int) {
     */
   def inc(): Bool = {
     if (n > 1) {
-      val wrap = value === UInt(n-1)
-      value := value + UInt(1)
+      val wrap = value === (n-1).asUInt
+      value := value + 1.U
       if (!isPow2(n)) {
-        when (wrap) { value := UInt(0) }
+        when (wrap) { value := 0.U }
       }
       wrap
     } else {
-      Bool(true)
+      true.B
     }
   }
 }
@@ -46,9 +46,9 @@ object Counter
     * maximum and the condition is true).
     *
     * @example {{{
-    * val countOn = Bool(true) // increment counter every clock cycle
+    * val countOn = true.B // increment counter every clock cycle
     * val (counterValue, counterWrap) = Counter(countOn, 4)
-    * when (counterValue === UInt(3)) {
+    * when (counterValue === 3.U) {
     *   ...
     * }
     * }}}
diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala
index 2f6effbd..fcda6943 100644
--- a/src/main/scala/chisel3/util/Decoupled.scala
+++ b/src/main/scala/chisel3/util/Decoupled.scala
@@ -32,7 +32,7 @@ object ReadyValidIO {
       * @return    dat.
       */
     def enq(dat: T): T = {
-      target.valid := Bool(true)
+      target.valid := true.B
       target.bits := dat
       dat
     }
@@ -40,7 +40,7 @@ object ReadyValidIO {
     /** Indicate no enqueue occurs.  Valid is set to false, and all bits are set to zero.
       */
     def noenq(): Unit = {
-      target.valid := Bool(false)
+      target.valid := false.B
       // We want the type from the following, not any existing binding.
       target.bits := target.bits.cloneType.fromBits(0.asUInt)
     }
@@ -51,14 +51,14 @@ object ReadyValidIO {
       * @return the data for this device,
       */
     def deq(): T = {
-      target.ready := Bool(true)
+      target.ready := true.B
       target.bits
     }
 
     /** Indicate no dequeue occurs. Ready is set to false
       */
     def nodeq(): Unit = {
-      target.ready := Bool(false)
+      target.ready := false.B
     }
   }
 }
@@ -144,7 +144,7 @@ class QueueIO[T <: Data](gen: T, entries: Int) extends Bundle
   /** I/O to enqueue data, is [[Chisel.DecoupledIO]]*/
   val deq = EnqIO(gen)
   /** The current amount of data in the queue */
-  val count = Output(UInt.width(log2Up(entries + 1)))
+  val count = Output(UInt(log2Up(entries + 1).W))
 
   override def cloneType = new QueueIO(gen, entries).asInstanceOf[this.type]
 }
@@ -177,7 +177,7 @@ extends Module(override_reset=override_reset) {
   val ram = Mem(entries, gen)
   val enq_ptr = Counter(entries)
   val deq_ptr = Counter(entries)
-  val maybe_full = Reg(init=Bool(false))
+  val maybe_full = Reg(init=false.B)
 
   val ptr_match = enq_ptr.value === deq_ptr.value
   val empty = ptr_match && !maybe_full
@@ -201,16 +201,16 @@ extends Module(override_reset=override_reset) {
   io.deq.bits := ram(deq_ptr.value)
 
   if (flow) {
-    when (io.enq.valid) { io.deq.valid := Bool(true) }
+    when (io.enq.valid) { io.deq.valid := true.B }
     when (empty) {
       io.deq.bits := io.enq.bits
-      do_deq := Bool(false)
-      when (io.deq.ready) { do_enq := Bool(false) }
+      do_deq := false.B
+      when (io.deq.ready) { do_enq := false.B }
     }
   }
 
   if (pipe) {
-    when (io.deq.ready) { io.enq.ready := Bool(true) }
+    when (io.deq.ready) { io.enq.ready := true.B }
   }
 
   val ptr_diff = enq_ptr.value - deq_ptr.value
@@ -219,9 +219,9 @@ extends Module(override_reset=override_reset) {
   } else {
     io.count := Mux(ptr_match,
                     Mux(maybe_full,
-                      UInt(entries), UInt(0)),
+                      entries.asUInt, 0.U),
                     Mux(deq_ptr.value > enq_ptr.value,
-                      UInt(entries) + ptr_diff, ptr_diff))
+                      entries.asUInt + ptr_diff, ptr_diff))
   }
 }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 4d816a19..7f715ad4 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,6 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
-  implicit def intToUInt(x: Int): UInt = UInt(x)
-  implicit def booleanToBool(x: Boolean): Bool = Bool(x)
+  implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
+  implicit def booleanToBool(x: Boolean): Bool = x.asBool
 }
diff --git a/src/main/scala/chisel3/util/LFSR.scala b/src/main/scala/chisel3/util/LFSR.scala
index fedbf194..83dc907d 100644
--- a/src/main/scala/chisel3/util/LFSR.scala
+++ b/src/main/scala/chisel3/util/LFSR.scala
@@ -15,9 +15,9 @@ object LFSR16 {
     *
     * @param increment optional control to gate when the LFSR updates.
     */
-  def apply(increment: Bool = Bool(true)): UInt = {
+  def apply(increment: Bool = true.B): UInt = {
     val width = 16
-    val lfsr = Reg(init=UInt(1, width))
+    val lfsr = Reg(init=1.U(width.W))
     when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
     lfsr
   }
diff --git a/src/main/scala/chisel3/util/OneHot.scala b/src/main/scala/chisel3/util/OneHot.scala
index 53ba8c3d..7dd0c68b 100644
--- a/src/main/scala/chisel3/util/OneHot.scala
+++ b/src/main/scala/chisel3/util/OneHot.scala
@@ -35,7 +35,7 @@ object OHToUInt {
   * Multiple bits may be high in the input.
   */
 object PriorityEncoder {
-  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(UInt(_)))
+  def apply(in: Seq[Bool]): UInt = PriorityMux(in, (0 until in.size).map(_.asUInt))
   def apply(in: Bits): UInt = apply(in.toBools)
 }
 
@@ -44,9 +44,9 @@ object PriorityEncoder {
 object UIntToOH {
   def apply(in: UInt, width: Int = -1): UInt =
     if (width == -1) {
-      UInt(1) << in
+      1.U << in
     } else {
-      (UInt(1) << in(log2Up(width)-1,0))(width-1,0)
+      (1.U << in(log2Up(width)-1,0))(width-1,0)
     }
 }
 
@@ -55,8 +55,8 @@ object UIntToOH {
   */
 object PriorityEncoderOH {
   private def encode(in: Seq[Bool]): UInt = {
-    val outs = Seq.tabulate(in.size)(i => UInt(BigInt(1) << i, in.size))
-    PriorityMux(in :+ Bool(true), outs :+ UInt(0, in.size))
+    val outs = Seq.tabulate(in.size)(i => (BigInt(1) << i).asUInt(in.size.W))
+    PriorityMux(in :+ true.B, outs :+ 0.U(in.size.W))
   }
   def apply(in: Seq[Bool]): Seq[Bool] = {
     val enc = encode(in)
diff --git a/src/main/scala/chisel3/util/Reg.scala b/src/main/scala/chisel3/util/Reg.scala
index f41d789c..00005e3a 100644
--- a/src/main/scala/chisel3/util/Reg.scala
+++ b/src/main/scala/chisel3/util/Reg.scala
@@ -53,7 +53,7 @@ object ShiftRegister
     * @param n number of cycles to delay
     * @param en enable the shift
     */
-  def apply[T <: Data](in: T, n: Int, en: Bool = Bool(true)): T = {
+  def apply[T <: Data](in: T, n: Int, en: Bool = true.B): T = {
     // The order of tests reflects the expected use cases.
     if (n != 0) {
       RegEnable(apply(in, n-1, en), en)
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 3d153a2a..49a6f515 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -41,7 +41,7 @@ object Pipe
       out.bits <> enqBits
       out
     } else {
-      val v = Reg(Bool(), next=enqValid, init=Bool(false))
+      val v = Reg(Bool(), next=enqValid, init=false.B)
       val b = RegEnable(enqBits, enqValid)
       apply(v, b, latency-1)
     }
diff --git a/src/test/scala/chiselTests/Assert.scala b/src/test/scala/chiselTests/Assert.scala
index efc2e1e7..475e18f7 100644
--- a/src/test/scala/chiselTests/Assert.scala
+++ b/src/test/scala/chiselTests/Assert.scala
@@ -8,7 +8,7 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class FailingAssertTester() extends BasicTester {
-  assert(Bool(false))
+  assert(false.B)
   // Wait to come out of reset
   val (_, done) = Counter(!reset, 4)
   when (done) {
@@ -17,7 +17,7 @@ class FailingAssertTester() extends BasicTester {
 }
 
 class SucceedingAssertTester() extends BasicTester {
-  assert(Bool(true))
+  assert(true.B)
   // Wait to come out of reset
   val (_, done) = Counter(!reset, 4)
   when (done) {
@@ -27,8 +27,8 @@ class SucceedingAssertTester() extends BasicTester {
 
 class PipelinedResetModule extends Module {
   val io = IO(new Bundle { })
-  val a = Reg(init = UInt(0xbeef))
-  val b = Reg(init = UInt(0xbeef))
+  val a = Reg(init = 0xbeef.U)
+  val b = Reg(init = 0xbeef.U)
   assert(a === b)
 }
 
diff --git a/src/test/scala/chiselTests/BetterNamingTests.scala b/src/test/scala/chiselTests/BetterNamingTests.scala
index f5872adb..df23f0a2 100644
--- a/src/test/scala/chiselTests/BetterNamingTests.scala
+++ b/src/test/scala/chiselTests/BetterNamingTests.scala
@@ -9,14 +9,14 @@ import chisel3.util._
 // Defined outside of the class so we don't get $ in name
 class Other(w: Int) extends Module {
   val io = new Bundle {
-    val a = UInt(width = w)
+    val a = UInt(w.W)
   }
 }
 class PerNameIndexing(count: Int) extends Module {
   val io = new Bundle { }
 
   val wires = Seq.tabulate(count) { i => Module(new Other(i)) }
-  val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(width = i), 16)) }
+  val queues = Seq.tabulate(count) { i => Module(new Queue(UInt(i.W), 16)) }
 }
 
 // Note this only checks Iterable[Chisel.Data] which excludes Maps
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index d8821134..8b4cf157 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -37,11 +37,11 @@ class BlackBoxTester extends BasicTester {
   val blackBoxPos = Module(new BlackBoxInverter)
   val blackBoxNeg = Module(new BlackBoxInverter)
 
-  blackBoxPos.io.in := UInt(1)
-  blackBoxNeg.io.in := UInt(0)
+  blackBoxPos.io.in := 1.U
+  blackBoxNeg.io.in := 0.U
 
-  assert(blackBoxNeg.io.out === UInt(1))
-  assert(blackBoxPos.io.out === UInt(0))
+  assert(blackBoxNeg.io.out === 1.U)
+  assert(blackBoxPos.io.out === 0.U)
   stop()
 }
 
@@ -56,15 +56,15 @@ class MultiBlackBoxTester extends BasicTester {
   val blackBoxPassPos = Module(new BlackBoxPassthrough)
   val blackBoxPassNeg = Module(new BlackBoxPassthrough)
 
-  blackBoxInvPos.io.in := UInt(1)
-  blackBoxInvNeg.io.in := UInt(0)
-  blackBoxPassPos.io.in := UInt(1)
-  blackBoxPassNeg.io.in := UInt(0)
+  blackBoxInvPos.io.in := 1.U
+  blackBoxInvNeg.io.in := 0.U
+  blackBoxPassPos.io.in := 1.U
+  blackBoxPassNeg.io.in := 0.U
 
-  assert(blackBoxInvNeg.io.out === UInt(1))
-  assert(blackBoxInvPos.io.out === UInt(0))
-  assert(blackBoxPassNeg.io.out === UInt(0))
-  assert(blackBoxPassPos.io.out === UInt(1))
+  assert(blackBoxInvNeg.io.out === 1.U)
+  assert(blackBoxInvPos.io.out === 0.U)
+  assert(blackBoxPassNeg.io.out === 0.U)
+  assert(blackBoxPassPos.io.out === 1.U)
   stop()
 }
 
@@ -72,14 +72,14 @@ class BlackBoxWithClockTester extends BasicTester {
   val blackBox = Module(new BlackBoxRegister)
   val model = Reg(Bool())
 
-  val (cycles, end) = Counter(Bool(true), 15)
+  val (cycles, end) = Counter(true.B, 15)
 
   val impetus = cycles(0)
   blackBox.io.clock := clock
   blackBox.io.in := impetus
   model := impetus
 
-  when(cycles > UInt(0)) {
+  when(cycles > 0.U) {
     assert(blackBox.io.out === model)
   }
   when(end) { stop() }
@@ -121,16 +121,16 @@ class BlackBoxWithParamsTester extends BasicTester {
   val blackBoxTypeParamBit = Module(new BlackBoxTypeParam(1, "bit"))
   val blackBoxTypeParamWord = Module(new BlackBoxTypeParam(32, "bit [31:0]"))
 
-  val (cycles, end) = Counter(Bool(true), 4)
+  val (cycles, end) = Counter(true.B, 4)
 
-  assert(blackBoxOne.io.out  === UInt(1))
-  assert(blackBoxFour.io.out === UInt(4))
-  assert(blackBoxStringParamOne.io.out === UInt(1))
-  assert(blackBoxStringParamTwo.io.out === UInt(2))
-  assert(blackBoxRealParamOne.io.out === UInt(0x3ff0000000000000L))
-  assert(blackBoxRealParamNeg.io.out === UInt(BigInt("bff0000000000000", 16)))
-  assert(blackBoxTypeParamBit.io.out === UInt(1))
-  assert(blackBoxTypeParamWord.io.out === UInt("hdeadbeef", 32))
+  assert(blackBoxOne.io.out  === 1.U)
+  assert(blackBoxFour.io.out === 4.U)
+  assert(blackBoxStringParamOne.io.out === 1.U)
+  assert(blackBoxStringParamTwo.io.out === 2.U)
+  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
+  assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
+  assert(blackBoxTypeParamBit.io.out === 1.U)
+  assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
 
   when(end) { stop() }
 }
diff --git a/src/test/scala/chiselTests/BundleWire.scala b/src/test/scala/chiselTests/BundleWire.scala
index 5b38ff6e..0faab9d0 100644
--- a/src/test/scala/chiselTests/BundleWire.scala
+++ b/src/test/scala/chiselTests/BundleWire.scala
@@ -8,8 +8,8 @@ import chisel3.testers.BasicTester
 //import chisel3.core.ExplicitCompileOptions.Strict
 
 class Coord extends Bundle {
-  val x = UInt.width( 32)
-  val y = UInt.width( 32)
+  val x = UInt(32.W)
+  val y = UInt(32.W)
 }
 
 class BundleWire(n: Int) extends Module {
@@ -26,12 +26,12 @@ class BundleWire(n: Int) extends Module {
 
 class BundleToUnitTester extends BasicTester {
   val bundle1 = Wire(new Bundle {
-    val a = UInt(width = 4)
-    val b = UInt(width = 4)
+    val a = UInt(4.W)
+    val b = UInt(4.W)
   })
   val bundle2 = Wire(new Bundle {
-    val a = UInt(width = 2)
-    val b = UInt(width = 6)
+    val a = UInt(2.W)
+    val b = UInt(6.W)
   })
 
   // 0b00011011 split as 0001 1011 and as 00 011011
@@ -47,11 +47,11 @@ class BundleToUnitTester extends BasicTester {
 
 class BundleWireTester(n: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new BundleWire(n))
-  dut.io.in.x := UInt(x)
-  dut.io.in.y := UInt(y)
+  dut.io.in.x := x.asUInt
+  dut.io.in.y := y.asUInt
   for (elt <- dut.io.outs) {
-    assert(elt.x === UInt(x))
-    assert(elt.y === UInt(y))
+    assert(elt.x === x.asUInt)
+    assert(elt.y === y.asUInt)
   }
   stop()
 }
diff --git a/src/test/scala/chiselTests/Clock.scala b/src/test/scala/chiselTests/Clock.scala
index 79dd2de4..78d60ed2 100644
--- a/src/test/scala/chiselTests/Clock.scala
+++ b/src/test/scala/chiselTests/Clock.scala
@@ -10,7 +10,7 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class ClockAsUIntTester extends BasicTester {
-  assert(Bool(true).asClock.asUInt === UInt(1))
+  assert(true.B.asClock.asUInt === 1.U)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/CompileOptionsTest.scala b/src/test/scala/chiselTests/CompileOptionsTest.scala
index 57ceff3f..cc0a966c 100644
--- a/src/test/scala/chiselTests/CompileOptionsTest.scala
+++ b/src/test/scala/chiselTests/CompileOptionsTest.scala
@@ -27,12 +27,12 @@ class CompileOptionsSpec extends ChiselFlatSpec {
   }
 
   class SmallBundle extends Bundle {
-    val f1 = UInt(width = 4)
-    val f2 = UInt(width = 5)
+    val f1 = UInt(4.W)
+    val f2 = UInt(5.W)
     override def cloneType: this.type = (new SmallBundle).asInstanceOf[this.type]
   }
   class BigBundle extends SmallBundle {
-    val f3 = UInt(width = 6)
+    val f3 = UInt(6.W)
     override def cloneType: this.type = (new BigBundle).asInstanceOf[this.type]
   }
 
@@ -73,7 +73,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
           val in = Input(new SmallBundle)
           val out = Output(new BigBundle)
         })
-        val badReg = Reg(UInt(7, width=4))
+        val badReg = Reg(7.U(4.W))
       }
       elaborate { new CreateRegFromBoundTypeModule() }
     }
@@ -87,7 +87,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
         val in = Input(new SmallBundle)
         val out = Output(new BigBundle)
       })
-      val badReg = Reg(UInt(7, width=4))
+      val badReg = Reg(7.U(4.W))
     }
     elaborate { new CreateRegFromBoundTypeModule() }
   }
@@ -97,7 +97,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class RequireIOWrapModule extends Module {
       val io = IO(new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       })
       io.out := io.in(1)
@@ -110,7 +110,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class RequireIOWrapModule extends Module {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
       io.out := io.in(1)
@@ -124,7 +124,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class RequireIOWrapModule extends Module {
         val io = new Bundle {
-          val in = UInt(width = 32).asInput
+          val in = UInt(32.W).asInput
           val out = Bool().asOutput
         }
         io.out := io.in(1)
@@ -141,8 +141,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
-          val in = Input(UInt(width = 3))
-          val out = Output(UInt(width = 4))
+          val in = Input(UInt(3.W))
+          val out = Output(UInt(4.W))
         })
       }
       class SwappedConnectionModule extends SimpleModule {
@@ -158,8 +158,8 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
-        val in = Input(UInt(width = 3))
-        val out = Output(UInt(width = 4))
+        val in = Input(UInt(3.W))
+        val out = Output(UInt(4.W))
       })
     }
     class SwappedConnectionModule extends SimpleModule {
@@ -177,15 +177,15 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
       class SimpleModule extends Module {
         val io = IO(new Bundle {
-          val in = Input(UInt(width = 3))
-          val out = Output(UInt(width = 4))
+          val in = Input(UInt(3.W))
+          val out = Output(UInt(4.W))
         })
-        val noDir = Wire(UInt(width = 3))
+        val noDir = Wire(UInt(3.W))
       }
 
       class DirectionLessConnectionModule extends SimpleModule {
-        val a = UInt(0, width = 3)
-        val b = Wire(UInt(width = 3))
+        val a = 0.U(3.W)
+        val b = Wire(UInt(3.W))
         val child = Module(new SimpleModule)
         b := child.noDir
       }
@@ -198,15 +198,15 @@ class CompileOptionsSpec extends ChiselFlatSpec {
 
     class SimpleModule extends Module {
       val io = IO(new Bundle {
-        val in = Input(UInt(width = 3))
-        val out = Output(UInt(width = 4))
+        val in = Input(UInt(3.W))
+        val out = Output(UInt(4.W))
       })
-      val noDir = Wire(UInt(width = 3))
+      val noDir = Wire(UInt(3.W))
     }
 
     class DirectionLessConnectionModule extends SimpleModule {
-      val a = UInt(0, width = 3)
-      val b = Wire(UInt(width = 3))
+      val a = 0.U(3.W)
+      val b = Wire(UInt(3.W))
       val child = Module(new SimpleModule)
       b := child.noDir
     }
@@ -217,7 +217,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends StrictModule {
       val io = IO(new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       })
       io.out := io.in(1)
@@ -231,7 +231,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     implicit val strictWithoutIOWrap = StrictWithoutIOWrap
     class RequireIOWrapModule extends NotStrictModule {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
       io.out := io.in(1)
@@ -246,7 +246,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
       implicit val strictWithoutIOWrap = StrictWithoutIOWrap
       class RequireIOWrapModule extends StrictModule {
         val io = new Bundle {
-          val in = UInt(width = 32).asInput
+          val in = UInt(32.W).asInput
           val out = Bool().asOutput
         }
         io.out := io.in(1)
@@ -274,7 +274,7 @@ class CompileOptionsSpec extends ChiselFlatSpec {
     }
     class NotIOWrapModule extends Module()(StrictNotIOWrap.CompileOptions) {
       val io = new Bundle {
-        val in = UInt(width = 32).asInput
+        val in = UInt(32.W).asInput
         val out = Bool().asOutput
       }
     }
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index c5a23f82..f7484501 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -17,28 +17,28 @@ class Complex[T <: Data](val re: T, val im: T) extends Bundle {
 class ComplexAssign(w: Int) extends Module {
   val io = IO(new Bundle {
     val e   = Input(Bool())
-    val in  = Input(new Complex(UInt.width(w), UInt.width(w)))
-    val out = Output(new Complex(UInt.width(w), UInt.width(w)))
+    val in  = Input(new Complex(UInt(w.W), UInt(w.W)))
+    val out = Output(new Complex(UInt(w.W), UInt(w.W)))
   })
   when (io.e) {
-    val tmp = Wire(new Complex(UInt.width(w), UInt.width(w)))
+    val tmp = Wire(new Complex(UInt(w.W), UInt(w.W)))
     tmp := io.in
     io.out.re := tmp.re
     io.out.im := tmp.im
   } .otherwise {
-    io.out.re := UInt(0)
-    io.out.im := UInt(0)
+    io.out.re := 0.U
+    io.out.im := 0.U
   }
 }
 
 class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), enList.size)
+  val (cnt, wrap) = Counter(true.B, enList.size)
   val dut = Module(new ComplexAssign(32))
-  dut.io.in.re := UInt(re)
-  dut.io.in.im := UInt(im)
+  dut.io.in.re := re.asUInt
+  dut.io.in.im := im.asUInt
   dut.io.e := Vec(enList.map(Bool(_)))(cnt)
-  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, UInt(0))
-  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, UInt(0))
+  val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U)
+  val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U)
   assert(re_correct && im_correct)
   when(wrap) {
     stop()
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index 69d8a44a..cccd8c0e 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -11,18 +11,18 @@ import chisel3.util._
 
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
-  when(Bool(true)) { cnt.inc() }
+  when(true.B) { cnt.inc() }
   when(cnt.value === UInt(max-1)) {
     stop()
   }
 }
 
 class EnableTester(seed: Int) extends BasicTester {
-  val ens = Reg(init = UInt(seed))
+  val ens = Reg(init = seed.asUInt)
   ens := ens >> 1
 
   val (cntEnVal, _) = Counter(ens(0), 32)
-  val (_, done) = Counter(Bool(true), 33)
+  val (_, done) = Counter(true.B, 33)
 
   when(done) {
     assert(cntEnVal === UInt(popCount(seed)))
@@ -31,7 +31,7 @@ class EnableTester(seed: Int) extends BasicTester {
 }
 
 class WrapTester(max: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), max)
+  val (cnt, wrap) = Counter(true.B, max)
   when(wrap) {
     assert(cnt === UInt(max - 1))
     stop()
diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala
index b50a80c0..ff73a676 100644
--- a/src/test/scala/chiselTests/Decoder.scala
+++ b/src/test/scala/chiselTests/Decoder.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 
 class Decoder(bitpats: List[String]) extends Module {
   val io = IO(new Bundle {
-    val inst  = Input(UInt.width(32))
+    val inst  = Input(UInt(32.W))
     val matched = Output(Bool())
   })
   io.matched := Vec(bitpats.map(BitPat(_) === io.inst)).reduce(_||_)
@@ -20,11 +20,11 @@ class Decoder(bitpats: List[String]) extends Module {
 
 class DecoderTester(pairs: List[(String, String)]) extends BasicTester {
   val (insts, bitpats) = pairs.unzip
-  val (cnt, wrap) = Counter(Bool(true), pairs.size)
+  val (cnt, wrap) = Counter(true.B, pairs.size)
   val dut = Module(new Decoder(bitpats))
-  dut.io.inst := Vec(insts.map(UInt(_)))(cnt)
+  dut.io.inst := Vec(insts.map(_.asUInt))(cnt)
   when(!dut.io.matched) {
-    assert(cnt === UInt(0))
+    assert(cnt === 0.U)
     stop()
   }
   when(wrap) {
diff --git a/src/test/scala/chiselTests/Direction.scala b/src/test/scala/chiselTests/Direction.scala
index 949b92ed..c3400013 100644
--- a/src/test/scala/chiselTests/Direction.scala
+++ b/src/test/scala/chiselTests/Direction.scala
@@ -9,17 +9,17 @@ import chisel3.testers.BasicTester
 
 class DirectionHaver extends Module {
   val io = IO(new Bundle {
-    val in = Input(UInt.width(32))
-    val out = Output(UInt.width(32))
+    val in = Input(UInt(32.W))
+    val out = Output(UInt(32.W))
   })
 }
 
 class GoodDirection extends DirectionHaver {
-  io.out := UInt(0)
+  io.out := 0.U
 }
 
 class BadDirection extends DirectionHaver {
-  io.in := UInt(0)
+  io.in := 0.U
 }
 
 class DirectionSpec extends ChiselPropSpec with ShouldMatchers {
diff --git a/src/test/scala/chiselTests/EnableShiftRegister.scala b/src/test/scala/chiselTests/EnableShiftRegister.scala
index 5f3e0dd1..6dc4aac6 100644
--- a/src/test/scala/chiselTests/EnableShiftRegister.scala
+++ b/src/test/scala/chiselTests/EnableShiftRegister.scala
@@ -6,14 +6,14 @@ import chisel3.testers.BasicTester
 
 class EnableShiftRegister extends Module {
   val io = IO(new Bundle {
-    val in    = Input(UInt.width(4))
+    val in    = Input(UInt(4.W))
     val shift = Input(Bool())
-    val out   = Output(UInt.width(4))
+    val out   = Output(UInt(4.W))
   })
-  val r0 = Reg(init = UInt(0, 4))
-  val r1 = Reg(init = UInt(0, 4))
-  val r2 = Reg(init = UInt(0, 4))
-  val r3 = Reg(init = UInt(0, 4))
+  val r0 = Reg(init = 0.U(4.W))
+  val r1 = Reg(init = 0.U(4.W))
+  val r2 = Reg(init = 0.U(4.W))
+  val r3 = Reg(init = 0.U(4.W))
   when(io.shift) {
     r0 := io.in
     r1 := r0
diff --git a/src/test/scala/chiselTests/GCD.scala b/src/test/scala/chiselTests/GCD.scala
index d683ce34..c20d26ad 100644
--- a/src/test/scala/chiselTests/GCD.scala
+++ b/src/test/scala/chiselTests/GCD.scala
@@ -9,14 +9,14 @@ import org.scalatest.prop._
 
 class GCD extends Module {
   val io = IO(new Bundle {
-    val a  = Input(UInt.width(32))
-    val b  = Input(UInt.width(32))
+    val a  = Input(UInt(32.W))
+    val b  = Input(UInt(32.W))
     val e  = Input(Bool())
-    val z  = Output(UInt.width(32))
+    val z  = Output(UInt(32.W))
     val v  = Output(Bool())
   })
-  val x = Reg(UInt.width( 32))
-  val y = Reg(UInt.width( 32))
+  val x = Reg(UInt(32.W))
+  val y = Reg(UInt(32.W))
   when (x > y)   { x := x -% y }
   .otherwise     { y := y -% x }
   when (io.e) { x := io.a; y := io.b }
@@ -30,7 +30,7 @@ class GCDTester(a: Int, b: Int, z: Int) extends BasicTester {
   dut.io.a := a.U
   dut.io.b := b.U
   dut.io.e := first
-  when(first) { first := Bool(false) }
+  when(first) { first := false.B }
   when(!first && dut.io.v) {
     assert(dut.io.z === z.U)
     stop()
diff --git a/src/test/scala/chiselTests/IOCompatibility.scala b/src/test/scala/chiselTests/IOCompatibility.scala
index 552fe776..521e895d 100644
--- a/src/test/scala/chiselTests/IOCompatibility.scala
+++ b/src/test/scala/chiselTests/IOCompatibility.scala
@@ -7,19 +7,19 @@ import chisel3.core.Binding.BindingException
 import org.scalatest._
 
 class IOCSimpleIO extends Bundle {
-  val in  = Input(UInt(width=32))
-  val out = Output(UInt(width=32))
+  val in  = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
 }
 
 class IOCPlusOne extends Module {
   val io = IO(new IOCSimpleIO)
-  io.out := io.in + UInt(1)
+  io.out := io.in + 1.U
 }
 
 class IOCModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Vec(n, Input(UInt(width=32)))
-    val outs = Vec(n, Output(UInt(width=32)))
+    val ins  = Vec(n, Input(UInt(32.W)))
+    val outs = Vec(n, Output(UInt(32.W)))
   })
   val pluses = Vec.fill(n){ Module(new IOCPlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/LFSR16.scala b/src/test/scala/chiselTests/LFSR16.scala
index b13b67e3..09beddb9 100644
--- a/src/test/scala/chiselTests/LFSR16.scala
+++ b/src/test/scala/chiselTests/LFSR16.scala
@@ -9,9 +9,9 @@ import chisel3.util._
 class LFSR16 extends Module {
   val io = IO(new Bundle {
     val inc = Input(Bool())
-    val out = Output(UInt.width(16))
+    val out = Output(UInt(16.W))
   })
-  val res = Reg(init = UInt(1, 16))
+  val res = Reg(init = 1.U(16.W))
   when (io.inc) {
     val nxt_res = Cat(res(0)^res(2)^res(3)^res(5), res(15,1))
     res := nxt_res
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index 1d09f3c5..befbf010 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -7,21 +7,21 @@ import chisel3.testers.BasicTester
 
 class MemorySearch extends Module {
   val io = IO(new Bundle {
-    val target  = Input(UInt.width(4))
+    val target  = Input(UInt(4.W))
     val en      = Input(Bool())
     val done    = Output(Bool())
-    val address = Output(UInt.width(3))
+    val address = Output(UInt(3.W))
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
-  val index = Reg(init = UInt(0, width = 3))
+  val index = Reg(init = 0.U(3.W))
   val elts  = Vec(vals.map(UInt(_,4)))
-  // val elts  = Mem(UInt(width = 32), 8) TODO ????
+  // val elts  = Mem(UInt(32.W), 8) TODO ????
   val elt  = elts(index)
-  val end  = !io.en && ((elt === io.target) || (index === UInt(7)))
+  val end  = !io.en && ((elt === io.target) || (index === 7.U))
   when (io.en) {
-    index := UInt(0)
+    index := 0.U
   } .elsewhen (!end) {
-    index := index +% UInt(1)
+    index := index +% 1.U
   }
   io.done    := end
   io.address := index
diff --git a/src/test/scala/chiselTests/Module.scala b/src/test/scala/chiselTests/Module.scala
index c902d073..4f043f0a 100644
--- a/src/test/scala/chiselTests/Module.scala
+++ b/src/test/scala/chiselTests/Module.scala
@@ -5,8 +5,8 @@ package chiselTests
 import chisel3._
 
 class SimpleIO extends Bundle {
-  val in  = Input(UInt.width(32))
-  val out = Output(UInt.width(32))
+  val in  = Input(UInt(32.W))
+  val out = Output(UInt(32.W))
 }
 
 class PlusOne extends Module {
@@ -16,8 +16,8 @@ class PlusOne extends Module {
 
 class ModuleVec(val n: Int) extends Module {
   val io = IO(new Bundle {
-    val ins  = Input(Vec(n, UInt(32)))
-    val outs = Output(Vec(n, UInt(32)))
+    val ins  = Input(Vec(n, 32.U))
+    val outs = Output(Vec(n, 32.U))
   })
   val pluses = Vec.fill(n){ Module(new PlusOne).io }
   for (i <- 0 until n) {
diff --git a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
index f8206b9c..27cf4a5f 100644
--- a/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
+++ b/src/test/scala/chiselTests/ModuleExplicitResetSpec.scala
@@ -6,13 +6,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec  {
 
   "A Module with an explicit reset in compatibility mode" should "elaborate" in {
     import Chisel._
-    val myReset = Bool(true)
+    val myReset = true.B
     class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
       val io = new Bundle {
         val done = Bool(OUTPUT)
       }
 
-      io.done := Bool(false)
+      io.done := false.B
     }
 
     elaborate {
@@ -22,13 +22,13 @@ class ModuleExplicitResetSpec extends ChiselFlatSpec  {
 
   "A Module with an explicit reset in non-compatibility mode" should "elaborate" in {
     import chisel3._
-    val myReset = Bool(true)
+    val myReset = true.B
     class ModuleExplicitReset(reset: Bool) extends Module(_reset = reset) {
       val io = IO(new Bundle {
-        val done = Bool(OUTPUT)
+        val done = Output(Bool())
       })
 
-      io.done := Bool(false)
+      io.done := false.B
     }
 
     elaborate {
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index 26ee4e03..f0b2aa21 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -9,8 +9,8 @@ import chisel3.testers.BasicTester
 
 class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
-    val x   = Input(UInt.width(w))
-    val y   = Input(UInt.width(w))
+    val x   = Input(UInt(w.W))
+    val y   = Input(UInt(w.W))
     val z   = Output(UInt.width(2 * w))
   })
   val tbl = Vec(
@@ -24,8 +24,8 @@ class MulLookup(val w: Int) extends Module {
 
 class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
-  dut.io.x := UInt(x)
-  dut.io.y := UInt(y)
+  dut.io.x := x.asUInt
+  dut.io.y := y.asUInt
   assert(dut.io.z === UInt(x * y))
   stop()
 }
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index 397ea4c2..fbe57da5 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -9,10 +9,10 @@ import chisel3.testers.BasicTester
 import chisel3.util._
 
 class LastAssignTester() extends BasicTester {
-  val countOnClockCycles = Bool(true)
+  val countOnClockCycles = true.B
   val (cnt, wrap) = Counter(countOnClockCycles,2)
 
-  val test = Wire(UInt.width(4))
+  val test = Wire(UInt(4.W))
   assert(test === 7.U)  // allow read references before assign references
 
   test := 13.U
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index 8e4c7579..d1b9152d 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -20,7 +20,7 @@ class OptionBundleModule(hasIn: Boolean) extends Module {
   if (hasIn) {
     io.out := io.in.get
   } else {
-    io.out := Bool(false)
+    io.out := false.B
   }
 }
 
@@ -33,14 +33,14 @@ class SomeOptionBundleTester(expected: Boolean) extends BasicTester {
 
 class NoneOptionBundleTester() extends BasicTester {
   val mod = Module(new OptionBundleModule(false))
-  assert(mod.io.out === Bool(false))
+  assert(mod.io.out === false.B)
   stop()
 }
 
 class InvalidOptionBundleTester() extends BasicTester {
   val mod = Module(new OptionBundleModule(false))
-  mod.io.in.get := Bool(true)
-  assert(Bool(false))
+  mod.io.in.get := true.B
+  assert(false.B)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Padding.scala b/src/test/scala/chiselTests/Padding.scala
index 42df6802..6f256b64 100644
--- a/src/test/scala/chiselTests/Padding.scala
+++ b/src/test/scala/chiselTests/Padding.scala
@@ -6,9 +6,9 @@ import chisel3._
 
 class Padder extends Module {
   val io = IO(new Bundle {
-    val a   = Input(UInt.width(4))
-    val asp = Output(SInt.width(8))
-    val aup = Output(UInt.width(8))
+    val a   = Input(UInt(4.W))
+    val asp = Output(SInt(8.W))
+    val aup = Output(UInt(8.W))
   })
   io.asp := io.a.asSInt
   io.aup := io.a.asUInt
diff --git a/src/test/scala/chiselTests/ParameterizedModule.scala b/src/test/scala/chiselTests/ParameterizedModule.scala
index 14b21631..028b5baf 100644
--- a/src/test/scala/chiselTests/ParameterizedModule.scala
+++ b/src/test/scala/chiselTests/ParameterizedModule.scala
@@ -26,10 +26,10 @@ class ParameterizedModuleTester() extends BasicTester {
   val invert = Module(new ParameterizedModule(true))
   val noninvert = Module(new ParameterizedModule(false))
 
-  invert.io.in := Bool(true)
-  noninvert.io.in := Bool(true)
-  assert(invert.io.out === Bool(false))
-  assert(noninvert.io.out === Bool(true))
+  invert.io.in := true.B
+  noninvert.io.in := true.B
+  assert(invert.io.out === false.B)
+  assert(noninvert.io.out === true.B)
 
   stop()
 }
diff --git a/src/test/scala/chiselTests/PrintableSpec.scala b/src/test/scala/chiselTests/PrintableSpec.scala
index 12564a40..62784cff 100644
--- a/src/test/scala/chiselTests/PrintableSpec.scala
+++ b/src/test/scala/chiselTests/PrintableSpec.scala
@@ -67,7 +67,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "generate proper printf for simple Decimal printing" in {
     class MyModule extends BasicTester {
-      val myWire = Wire(init = UInt(1234))
+      val myWire = Wire(init = 1234.U)
       printf(p"myWire = ${Decimal(myWire)}")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -78,7 +78,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "handle printing literals" in {
     class MyModule extends BasicTester {
-      printf(Decimal(UInt(10, 32)))
+      printf(Decimal(10.U(32.W)))
     }
     val firrtl = Driver.emit(() => new MyModule)
     getPrintfs(firrtl) match {
@@ -102,11 +102,11 @@ class PrintableSpec extends FlatSpec with Matchers {
     // parent module
     class MySubModule extends Module {
       val io = new Bundle {
-        val fizz = UInt(width = 32)
+        val fizz = UInt(32.W)
       }
     }
     class MyBundle extends Bundle {
-      val foo = UInt(width = 32)
+      val foo = UInt(32.W)
       override def cloneType = (new MyBundle).asInstanceOf[this.type]
     }
     class MyModule extends BasicTester {
@@ -129,7 +129,7 @@ class PrintableSpec extends FlatSpec with Matchers {
   it should "handle printing ports of submodules" in {
     class MySubModule extends Module {
       val io = new Bundle {
-        val fizz = UInt(width = 32)
+        val fizz = UInt(32.W)
       }
     }
     class MyModule extends BasicTester {
@@ -144,8 +144,8 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "print UInts and SInts as Decimal by default" in {
     class MyModule extends BasicTester {
-      val myUInt = Wire(init = UInt(0))
-      val mySInt = Wire(init = SInt(-1))
+      val myUInt = Wire(init = 0.U)
+      val mySInt = Wire(init = -1.S)
       printf(p"$myUInt & $mySInt")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -156,8 +156,8 @@ class PrintableSpec extends FlatSpec with Matchers {
   }
   it should "print Vecs like Scala Seqs by default" in {
     class MyModule extends BasicTester {
-      val myVec = Wire(Vec(4, UInt(width = 32)))
-      myVec foreach (_ := UInt(0))
+      val myVec = Wire(Vec(4, UInt(32.W)))
+      myVec foreach (_ := 0.U)
       printf(p"$myVec")
     }
     val firrtl = Driver.emit(() => new MyModule)
@@ -170,11 +170,11 @@ class PrintableSpec extends FlatSpec with Matchers {
   it should "print Bundles like Scala Maps by default" in {
     class MyModule extends BasicTester {
       val myBun = Wire(new Bundle {
-        val foo = UInt(width = 32)
-        val bar = UInt(width = 32)
+        val foo = UInt(32.W)
+        val bar = UInt(32.W)
       })
-      myBun.foo := UInt(0)
-      myBun.bar := UInt(0)
+      myBun.foo := 0.U
+      myBun.bar := 0.U
       printf(p"$myBun")
     }
     val firrtl = Driver.emit(() => new MyModule)
diff --git a/src/test/scala/chiselTests/Printf.scala b/src/test/scala/chiselTests/Printf.scala
index 28b6132b..6a0569a2 100644
--- a/src/test/scala/chiselTests/Printf.scala
+++ b/src/test/scala/chiselTests/Printf.scala
@@ -8,7 +8,7 @@ import chisel3.util._
 import chisel3.testers.BasicTester
 
 class SinglePrintfTester() extends BasicTester {
-  val x = UInt(254)
+  val x = 254.U
   printf("x=%x", x)
   stop()
 }
@@ -19,8 +19,8 @@ class ASCIIPrintfTester() extends BasicTester {
 }
 
 class MultiPrintfTester() extends BasicTester {
-  val x = UInt(254)
-  val y = UInt(255)
+  val x = 254.U
+  val y = 255.U
   printf("x=%x y=%x", x, y)
   stop()
 }
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 90992c01..43e64fe7 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -17,7 +17,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of the same type and width as outType, if specified" in {
     class RegOutTypeWidthTester extends BasicTester {
-      val reg = Reg(t=UInt(width=2), next=Wire(UInt(width=3)), init=UInt(20))
+      val reg = Reg(t=UInt(2.W), next=Wire(UInt(3.W)), init=20.U)
       reg.getWidth should be (2)
     }
     elaborate{ new RegOutTypeWidthTester }
@@ -25,13 +25,13 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of unknown width if outType is not specified and width is not forced" in {
     class RegUnknownWidthTester extends BasicTester {
-      val reg1 = Reg(next=Wire(UInt(width=3)), init=UInt(20))
+      val reg1 = Reg(next=Wire(UInt(3.W)), init=20.U)
       reg1.isWidthKnown should be (false)
       DataMirror.widthOf(reg1).known should be (false)
-      val reg2 = Reg(init=UInt(20))
+      val reg2 = Reg(init=20.U)
       reg2.isWidthKnown should be (false)
       DataMirror.widthOf(reg2).known should be (false)
-      val reg3 = Reg(next=Wire(UInt(width=3)), init=UInt(5))
+      val reg3 = Reg(next=Wire(UInt(3.W)), init=5.U)
       reg3.isWidthKnown should be (false)
       DataMirror.widthOf(reg3).known should be (false)
     }
@@ -40,7 +40,7 @@ class RegSpec extends ChiselFlatSpec {
 
   "A Reg" should "be of width of init if outType and next are missing and init is a literal of forced width" in {
     class RegForcedWidthTester extends BasicTester {
-      val reg2 = Reg(init=UInt(20, width=7))
+      val reg2 = Reg(init=20.U(7.W))
       reg2.getWidth should be (7)
     }
     elaborate{ new RegForcedWidthTester }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 6d5a0a76..ae99df59 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -8,18 +8,18 @@ import chisel3.util._
 class Risc extends Module {
   val io = IO(new Bundle {
     val isWr   = Input(Bool())
-    val wrAddr = Input(UInt.width(8))
-    val wrData = Input(Bits.width(32))
+    val wrAddr = Input(UInt(8.W))
+    val wrData = Input(Bits(32.W))
     val boot   = Input(Bool())
     val valid  = Output(Bool())
-    val out    = Output(Bits.width(32))
+    val out    = Output(Bits(32.W))
   })
   val memSize = 256
-  val file = Mem(memSize, Bits.width(32))
-  val code = Mem(memSize, Bits.width(32))
-  val pc   = Reg(init=UInt(0, 8))
+  val file = Mem(memSize, Bits(32.W))
+  val code = Mem(memSize, Bits(32.W))
+  val pc   = Reg(init=0.U(8.W))
 
-  val add_op :: imm_op :: Nil = Enum(Bits.width(8), 2)
+  val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2)
 
   val inst = code(pc)
   val op   = inst(31,24)
@@ -29,16 +29,16 @@ class Risc extends Module {
 
   val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
   val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
-  val rc = Wire(Bits.width(32))
+  val rc = Wire(Bits(32.W))
 
-  io.valid := Bool(false)
+  io.valid := false.B
   io.out   := 0.asUInt()
   rc       := 0.asUInt()
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
   } .elsewhen (io.boot) {
-    pc := UInt(0)
+    pc := 0.U
   } .otherwise {
     switch(op) {
       is(add_op) { rc := ra +% rb }
@@ -46,7 +46,7 @@ class Risc extends Module {
     }
     io.out := rc
     when (rci === 255.asUInt()) {
-      io.valid := Bool(true)
+      io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }
diff --git a/src/test/scala/chiselTests/SIntOps.scala b/src/test/scala/chiselTests/SIntOps.scala
index 392c4803..900eb074 100644
--- a/src/test/scala/chiselTests/SIntOps.scala
+++ b/src/test/scala/chiselTests/SIntOps.scala
@@ -7,22 +7,22 @@ import chisel3.testers.BasicTester
 
 class SIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(SInt.width(16))
-    val b = Input(SInt.width(16))
-    val addout = Output(SInt.width(16))
-    val subout = Output(SInt.width(16))
-    val timesout = Output(SInt.width(16))
-    val divout = Output(SInt.width(16))
-    val modout = Output(SInt.width(16))
-    val lshiftout = Output(SInt.width(16))
-    val rshiftout = Output(SInt.width(16))
+    val a = Input(SInt(16.W))
+    val b = Input(SInt(16.W))
+    val addout = Output(SInt(16.W))
+    val subout = Output(SInt(16.W))
+    val timesout = Output(SInt(16.W))
+    val divout = Output(SInt(16.W))
+    val modout = Output(SInt(16.W))
+    val lshiftout = Output(SInt(16.W))
+    val rshiftout = Output(SInt(16.W))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
     val noteqout = Output(Bool())
     val lesseqout = Output(Bool())
     val greateqout = Output(Bool())
-    val negout = Output(SInt.width(16))
+    val negout = Output(SInt(16.W))
   })
 
   val a = io.a
@@ -32,9 +32,9 @@ class SIntOps extends Module {
   io.subout := a -% b
   // TODO:
   //io.timesout := (a * b)(15, 0)
-  //io.divout := a / Mux(b === SInt(0), SInt(1), b)
+  //io.divout := a / Mux(b === 0.S, 1.S, b)
   //io.divout := (a / b)(15, 0)
-  //io.modout := SInt(0)
+  //io.modout := 0.S
   //io.lshiftout := (a << 12)(15, 0) //  (a << ub(3, 0))(15, 0).toSInt
   io.rshiftout := (a >> 8) // (a >> ub).toSInt
   io.lessout := a < b
@@ -44,7 +44,7 @@ class SIntOps extends Module {
   io.lesseqout := a <= b
   io.greateqout := a >= b
   // io.negout := -a(15, 0).toSInt
-  io.negout := (SInt(0) -% a)
+  io.negout := (0.S -% a)
 }
 
 /*
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index a72af928..ce8fd9fc 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -12,23 +12,23 @@ class ChiselStack(val depth: Int) extends Module {
     val push    = Input(Bool())
     val pop     = Input(Bool())
     val en      = Input(Bool())
-    val dataIn  = Input(UInt.width(32))
-    val dataOut = Output(UInt.width(32))
+    val dataIn  = Input(UInt(32.W))
+    val dataOut = Output(UInt(32.W))
   })
 
-  val stack_mem = Mem(depth, UInt.width(32))
+  val stack_mem = Mem(depth, UInt(32.W))
   val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
-  val out       = Reg(init = UInt(0, width = 32))
+  val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
-    when(io.push && (sp < UInt(depth))) {
+    when(io.push && (sp < depth.asUInt)) {
       stack_mem(sp) := io.dataIn
-      sp := sp +% UInt(1)
-    } .elsewhen(io.pop && (sp > UInt(0))) {
-      sp := sp -% UInt(1)
+      sp := sp +% 1.U
+    } .elsewhen(io.pop && (sp > 0.U)) {
+      sp := sp -% 1.U
     }
-    when (sp > UInt(0)) {
-      out := stack_mem(sp -% UInt(1))
+    when (sp > 0.U) {
+      out := stack_mem(sp -% 1.U)
     }
   }
   io.dataOut := out
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index 66a06435..ccfba499 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -14,10 +14,10 @@ class Tbl(w: Int, n: Int) extends Module {
     val wi  = Input(UInt.width(log2Up(n)))
     val ri  = Input(UInt.width(log2Up(n)))
     val we  = Input(Bool())
-    val  d  = Input(UInt.width(w))
-    val  o  = Output(UInt.width(w))
+    val  d  = Input(UInt(w.W))
+    val  o  = Output(UInt(w.W))
   })
-  val m = Mem(n, UInt.width(w))
+  val m = Mem(n, UInt(w.W))
   io.o := m(io.ri)
   when (io.we) {
     m(io.wi) := io.d
@@ -28,17 +28,17 @@ class Tbl(w: Int, n: Int) extends Module {
 }
 
 class TblTester(w: Int, n: Int, idxs: List[Int], values: List[Int]) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), idxs.size)
+  val (cnt, wrap) = Counter(true.B, idxs.size)
   val dut = Module(new Tbl(w, n))
-  val vvalues = Vec(values.map(UInt(_)))
-  val vidxs = Vec(idxs.map(UInt(_)))
-  val prev_idx = vidxs(cnt - UInt(1))
-  val prev_value = vvalues(cnt - UInt(1))
+  val vvalues = Vec(values.map(_.asUInt))
+  val vidxs = Vec(idxs.map(_.asUInt))
+  val prev_idx = vidxs(cnt - 1.U)
+  val prev_value = vvalues(cnt - 1.U)
   dut.io.wi := vidxs(cnt)
   dut.io.ri := prev_idx
-  dut.io.we := Bool(true) //TODO enSequence
+  dut.io.we := true.B //TODO enSequence
   dut.io.d := vvalues(cnt)
-  when (cnt > UInt(0)) {
+  when (cnt > 0.U) {
     when (prev_idx === vidxs(cnt)) {
       assert(dut.io.o === vvalues(cnt))
     } .otherwise {
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index b2e811d9..c0d64a43 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -25,13 +25,13 @@ class FinishTester extends BasicTester {
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
-  assert(test_wire === UInt(test_wire_override_value))
+  assert(test_wire === test_wire_override_value.asUInt)
 
   /** In finish we use last connect semantics to alter the test_wire in the circuit
     * with a new value
     */
   override def finish(): Unit = {
-    test_wire := UInt(test_wire_override_value)
+    test_wire := test_wire_override_value.asUInt
   }
 }
 
diff --git a/src/test/scala/chiselTests/UIntOps.scala b/src/test/scala/chiselTests/UIntOps.scala
index ad5aecd8..addd753f 100644
--- a/src/test/scala/chiselTests/UIntOps.scala
+++ b/src/test/scala/chiselTests/UIntOps.scala
@@ -8,15 +8,15 @@ import chisel3.testers.BasicTester
 
 class UIntOps extends Module {
   val io = IO(new Bundle {
-    val a = Input(UInt.width(16))
-    val b = Input(UInt.width(16))
-    val addout = Output(UInt.width(16))
-    val subout = Output(UInt.width(16))
-    val timesout = Output(UInt.width(16))
-    val divout = Output(UInt.width(16))
-    val modout = Output(UInt.width(16))
-    val lshiftout = Output(UInt.width(16))
-    val rshiftout = Output(UInt.width(16))
+    val a = Input(UInt(16.W))
+    val b = Input(UInt(16.W))
+    val addout = Output(UInt(16.W))
+    val subout = Output(UInt(16.W))
+    val timesout = Output(UInt(16.W))
+    val divout = Output(UInt(16.W))
+    val modout = Output(UInt(16.W))
+    val lshiftout = Output(UInt(16.W))
+    val rshiftout = Output(UInt(16.W))
     val lessout = Output(Bool())
     val greatout = Output(Bool())
     val eqout = Output(Bool())
@@ -31,10 +31,10 @@ class UIntOps extends Module {
   io.addout := a +% b
   io.subout := a -% b
   io.timesout := (a * b)(15, 0)
-  io.divout := a / Mux(b === UInt(0), UInt(1), b)
+  io.divout := a / Mux(b === 0.U, 1.U, b)
   // io.modout := a % b
   // TODO:
-  io.modout := UInt(0)
+  io.modout := 0.U
   io.lshiftout := (a << b(3, 0))(15, 0)
   io.rshiftout := a >> b
   io.lessout := a < b
@@ -78,7 +78,7 @@ class UIntOpsTester(c: UIntOps) extends Tester(c) {
 
 class GoodBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt.width(1))
+    val u = Input(UInt(1.W))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
@@ -86,7 +86,7 @@ class GoodBoolConversion extends Module {
 
 class BadBoolConversion extends Module {
   val io = IO(new Bundle {
-    val u = Input(UInt.width( 5))
+    val u = Input(UInt(5.W))
     val b = Output(Bool())
   })
   io.b := io.u.toBool
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 0d5a2188..90e337a8 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -13,7 +13,7 @@ import chisel3.util._
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
   val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
-    assert(a === UInt(b))
+    assert(a === b.asUInt)
   }
   stop()
 }
@@ -31,12 +31,12 @@ class TabulateTester(n: Int) extends BasicTester {
 }
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
-  val (cnt, wrap) = Counter(Bool(true), n*2)
+  val (cnt, wrap) = Counter(true.B, n*2)
   val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
-  when (cnt >= UInt(n)) {
-    val expected = cnt - UInt(n)
+  when (cnt >= n.asUInt) {
+    val expected = cnt - n.asUInt
     assert(shifter(0) === expected)
   }
   when (wrap) {
diff --git a/src/test/scala/chiselTests/VectorPacketIO.scala b/src/test/scala/chiselTests/VectorPacketIO.scala
index b8e3a154..bcf59e03 100644
--- a/src/test/scala/chiselTests/VectorPacketIO.scala
+++ b/src/test/scala/chiselTests/VectorPacketIO.scala
@@ -19,7 +19,7 @@ import chisel3.util._
   * IMPORTANT:  The canonical way to initialize a decoupled inteface is still being debated.
   */
 class Packet extends Bundle {
-  val header = UInt.width(1)
+  val header = UInt(1.W)
 }
 
 /**
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index 00b1e7de..c474430b 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -11,7 +11,7 @@ class VendingMachine extends Module {
     val dime   = Input(Bool())
     val valid  = Output(Bool())
   })
-  val c = UInt(5, width = 3)
+  val c = 5.U(3.W)
   val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
   val state = Reg(init = sIdle)
   when (state === sIdle) {
diff --git a/src/test/scala/chiselTests/When.scala b/src/test/scala/chiselTests/When.scala
index 6dc2dbac..d4491e13 100644
--- a/src/test/scala/chiselTests/When.scala
+++ b/src/test/scala/chiselTests/When.scala
@@ -11,44 +11,44 @@ import chisel3.util._
 
 class WhenTester() extends BasicTester {
   val cnt = Counter(4)
-  when(Bool(true)) { cnt.inc() }
-
-  val out = Wire(UInt.width(3))
-  when(cnt.value === UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value === UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value === UInt(2)) {
-    out := UInt(3)
+  when(true.B) { cnt.inc() }
+
+  val out = Wire(UInt(3.W))
+  when(cnt.value === 0.U) {
+    out := 1.U
+  } .elsewhen (cnt.value === 1.U) {
+    out := 2.U
+  } .elsewhen (cnt.value === 2.U) {
+    out := 3.U
   } .otherwise {
-    out := UInt(0)
+    out := 0.U
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + 1.U)
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === 3.U) {
     stop()
   }
 }
 
 class OverlappedWhenTester() extends BasicTester {
   val cnt = Counter(4)
-  when(Bool(true)) { cnt.inc() }
-
-  val out = Wire(UInt.width(3))
-  when(cnt.value <= UInt(0)) {
-    out := UInt(1)
-  } .elsewhen (cnt.value <= UInt(1)) {
-    out := UInt(2)
-  } .elsewhen (cnt.value <= UInt(2)) {
-    out := UInt(3)
+  when(true.B) { cnt.inc() }
+
+  val out = Wire(UInt(3.W))
+  when(cnt.value <= 0.U) {
+    out := 1.U
+  } .elsewhen (cnt.value <= 1.U) {
+    out := 2.U
+  } .elsewhen (cnt.value <= 2.U) {
+    out := 3.U
   } .otherwise {
-    out := UInt(0)
+    out := 0.U
   }
 
-  assert(out === cnt.value + UInt(1))
+  assert(out === cnt.value + 1.U)
 
-  when(cnt.value === UInt(3)) {
+  when(cnt.value === 3.U) {
     stop()
   }
 }
diff --git a/src/test/scala/cookbook/Bundle2UInt.scala b/src/test/scala/cookbook/Bundle2UInt.scala
index d74218a8..cb9498d1 100644
--- a/src/test/scala/cookbook/Bundle2UInt.scala
+++ b/src/test/scala/cookbook/Bundle2UInt.scala
@@ -11,17 +11,17 @@ import chisel3._
 class Bundle2UInt extends CookbookTester(0) {
   // Example
   class MyBundle extends Bundle {
-    val foo = UInt(width = 4)
-    val bar = UInt(width = 4)
+    val foo = UInt(4.W)
+    val bar = UInt(4.W)
   }
   val bundle = Wire(new MyBundle)
-  bundle.foo := UInt(0xc)
-  bundle.bar := UInt(0x3)
+  bundle.foo := 0xc.U
+  bundle.bar := 0x3.U
   val uint = bundle.asUInt
   printf(p"$uint") // 195
 
   // Test
-  assert(uint === UInt(0xc3))
+  assert(uint === 0xc3.U)
 }
 
 class Bundle2UIntSpec  extends CookbookSpec {
diff --git a/src/test/scala/cookbook/CookbookSpec.scala b/src/test/scala/cookbook/CookbookSpec.scala
index b244f3cf..6ecea446 100644
--- a/src/test/scala/cookbook/CookbookSpec.scala
+++ b/src/test/scala/cookbook/CookbookSpec.scala
@@ -18,7 +18,7 @@ abstract class CookbookTester(length: Int) extends BasicTester {
   // No IO allowed, cookbook tests must be self-contained
   override final val io = new Bundle { }
 
-  val (cycle, done) = Counter(Bool(true), length)
+  val (cycle, done) = Counter(true.B, length)
   when (done) { stop() }
 }
 
diff --git a/src/test/scala/cookbook/UInt2Bundle.scala b/src/test/scala/cookbook/UInt2Bundle.scala
index fbf7fe8a..3ce4eebf 100644
--- a/src/test/scala/cookbook/UInt2Bundle.scala
+++ b/src/test/scala/cookbook/UInt2Bundle.scala
@@ -11,16 +11,16 @@ import chisel3._
 class UInt2Bundle extends CookbookTester(0) {
   // Example
   class MyBundle extends Bundle {
-    val foo = UInt(width = 4)
-    val bar = UInt(width = 4)
+    val foo = UInt(4.W)
+    val bar = UInt(4.W)
   }
-  val uint = UInt(0xb4)
+  val uint = 0xb4.U
   val bundle = (new MyBundle).fromBits(uint)
   printf(p"$bundle") // Bundle(foo -> 11, bar -> 4)
 
   // Test
-  assert(bundle.foo === UInt(0xb))
-  assert(bundle.bar === UInt(0x4))
+  assert(bundle.foo === 0xb.U)
+  assert(bundle.bar === 0x4.U)
 }
 
 class UInt2BundleSpec extends CookbookSpec {
diff --git a/src/test/scala/cookbook/UInt2VecOfBool.scala b/src/test/scala/cookbook/UInt2VecOfBool.scala
index ad4a0334..09d538f9 100644
--- a/src/test/scala/cookbook/UInt2VecOfBool.scala
+++ b/src/test/scala/cookbook/UInt2VecOfBool.scala
@@ -11,15 +11,15 @@ import chisel3._
  */
 class UInt2VecOfBool extends CookbookTester(0) {
   // Example
-  val uint = UInt(0xc)
+  val uint = 0xc.U
   val vec = Vec(uint.toBools)
   printf(p"$vec") // Vec(0, 0, 1, 1)
 
   // Test
-  assert(vec(0) === Bool(false))
-  assert(vec(1) === Bool(false))
-  assert(vec(2) === Bool(true))
-  assert(vec(3) === Bool(true))
+  assert(vec(0) === false.B)
+  assert(vec(1) === false.B)
+  assert(vec(2) === true.B)
+  assert(vec(3) === true.B)
 }
 
 class UInt2VecOfBoolSpec extends CookbookSpec {
diff --git a/src/test/scala/cookbook/VecOfBool2UInt.scala b/src/test/scala/cookbook/VecOfBool2UInt.scala
index 5852120c..531e4e68 100644
--- a/src/test/scala/cookbook/VecOfBool2UInt.scala
+++ b/src/test/scala/cookbook/VecOfBool2UInt.scala
@@ -10,7 +10,7 @@ import chisel3._
  */
 class VecOfBool2UInt extends CookbookTester(0) {
   // Example
-  val vec = Vec(Bool(true), Bool(false), Bool(true), Bool(true))
+  val vec = Vec(true.B, false.B, true.B, true.B)
   val uint = vec.asUInt
   printf(p"$uint") // 13
   
@@ -18,7 +18,7 @@ class VecOfBool2UInt extends CookbookTester(0) {
    *
    * (remember leftmost Bool in Vec is low order bit)
    */
-  assert(UInt(0xd) === uint)
+  assert(0xd.U === uint)
 }
 
 class VecOfBool2UIntSpec  extends CookbookSpec {
-- 
cgit v1.2.3


From 73906fcc796b259c81d5df7733968b77fbb81ba8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:06:57 -0800
Subject: All remaining automatable regex re-styles

---
 src/main/scala/chisel3/package.scala           | 5 +++--
 src/test/scala/chiselTests/BitwiseOps.scala    | 4 ++--
 src/test/scala/chiselTests/ComplexAssign.scala | 2 +-
 src/test/scala/chiselTests/MemorySearch.scala  | 2 +-
 src/test/scala/chiselTests/OptionBundle.scala  | 4 ++--
 src/test/scala/chiselTests/Risc.scala          | 2 +-
 src/test/scala/chiselTests/Vec.scala           | 2 +-
 7 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 8b5b8a46..5b02be34 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -41,8 +41,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
     * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
     * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
-    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width)?\s*=\s*(\d+)\) => $1.U($2.W)
-    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1.U($2.W)
+    * (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
+    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1($3.W)
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index 08999a1b..b8efaccf 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -9,8 +9,8 @@ import chisel3.testers.BasicTester
 
 class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
-  val a = UInt(_a, w)
-  val b = UInt(_b, w)
+  val a = _a.asUInt(w.W)
+  val b = _b.asUInt(w.W)
   assert(~a === UInt(mask & ~_a))
   assert((a & b) === UInt(_a & _b))
   assert((a | b) === UInt(_a | _b))
diff --git a/src/test/scala/chiselTests/ComplexAssign.scala b/src/test/scala/chiselTests/ComplexAssign.scala
index f7484501..a13ec959 100644
--- a/src/test/scala/chiselTests/ComplexAssign.scala
+++ b/src/test/scala/chiselTests/ComplexAssign.scala
@@ -36,7 +36,7 @@ class ComplexAssignTester(enList: List[Boolean], re: Int, im: Int) extends Basic
   val dut = Module(new ComplexAssign(32))
   dut.io.in.re := re.asUInt
   dut.io.in.im := im.asUInt
-  dut.io.e := Vec(enList.map(Bool(_)))(cnt)
+  dut.io.e := Vec(enList.map(_.asBool))(cnt)
   val re_correct = dut.io.out.re === Mux(dut.io.e, dut.io.in.re, 0.U)
   val im_correct = dut.io.out.im === Mux(dut.io.e, dut.io.in.im, 0.U)
   assert(re_correct && im_correct)
diff --git a/src/test/scala/chiselTests/MemorySearch.scala b/src/test/scala/chiselTests/MemorySearch.scala
index befbf010..4cbedf58 100644
--- a/src/test/scala/chiselTests/MemorySearch.scala
+++ b/src/test/scala/chiselTests/MemorySearch.scala
@@ -14,7 +14,7 @@ class MemorySearch extends Module {
   })
   val vals  = Array(0, 4, 15, 14, 2, 5, 13)
   val index = Reg(init = 0.U(3.W))
-  val elts  = Vec(vals.map(UInt(_,4)))
+  val elts  = Vec(vals.map(_.asUInt(4.W)))
   // val elts  = Mem(UInt(32.W), 8) TODO ????
   val elt  = elts(index)
   val end  = !io.en && ((elt === io.target) || (index === 7.U))
diff --git a/src/test/scala/chiselTests/OptionBundle.scala b/src/test/scala/chiselTests/OptionBundle.scala
index d1b9152d..2ac661ea 100644
--- a/src/test/scala/chiselTests/OptionBundle.scala
+++ b/src/test/scala/chiselTests/OptionBundle.scala
@@ -26,8 +26,8 @@ class OptionBundleModule(hasIn: Boolean) extends Module {
 
 class SomeOptionBundleTester(expected: Boolean) extends BasicTester {
   val mod = Module(new OptionBundleModule(true))
-  mod.io.in.get := Bool(expected)
-  assert(mod.io.out === Bool(expected))
+  mod.io.in.get := expected.asBool
+  assert(mod.io.out === expected.asBool)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index ae99df59..744e3631 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -73,7 +73,7 @@ class RiscTester(c: Risc) extends Tester(c) {
     step(1)
   }
   def I (op: UInt, rc: Int, ra: Int, rb: Int) = {
-    // val cr = Cat(op, UInt(rc, 8), UInt(ra, 8), UInt(rb, 8)).litValue()
+    // val cr = Cat(op, rc.asUInt(8.W), ra.asUInt(8.W), rb.asUInt(8.W)).litValue()
     val cr = op.litValue() << 24 | rc << 16 | ra << 8 | rb
     println("I = " + cr)    // scalastyle:ignore regex
     cr
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 90e337a8..c621c1e1 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -11,7 +11,7 @@ import chisel3.util._
 //import chisel3.core.ExplicitCompileOptions.Strict
 
 class ValueTester(w: Int, values: List[Int]) extends BasicTester {
-  val v = Vec(values.map(UInt(_, width = w))) // TODO: does this need a Wire? Why no error?
+  val v = Vec(values.map(_.asUInt(w.W))) // TODO: does this need a Wire? Why no error?
   for ((a,b) <- v.zip(values)) {
     assert(a === b.asUInt)
   }
-- 
cgit v1.2.3


From 37a569372c70a651c813d0beb44124878a596e73 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:16:40 -0800
Subject: Fix all deprecations from new style

---
 src/test/scala/chiselTests/BitwiseOps.scala       | 8 ++++----
 src/test/scala/chiselTests/Counter.scala          | 6 +++---
 src/test/scala/chiselTests/MulLookup.scala        | 6 +++---
 src/test/scala/chiselTests/Stack.scala            | 2 +-
 src/test/scala/chiselTests/Tbl.scala              | 4 ++--
 src/test/scala/chiselTests/TesterDriverSpec.scala | 2 +-
 src/test/scala/chiselTests/Vec.scala              | 8 ++++----
 7 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala
index b8efaccf..1292222c 100644
--- a/src/test/scala/chiselTests/BitwiseOps.scala
+++ b/src/test/scala/chiselTests/BitwiseOps.scala
@@ -11,10 +11,10 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester {
   val mask = (1 << w) - 1
   val a = _a.asUInt(w.W)
   val b = _b.asUInt(w.W)
-  assert(~a === UInt(mask & ~_a))
-  assert((a & b) === UInt(_a & _b))
-  assert((a | b) === UInt(_a | _b))
-  assert((a ^ b) === UInt(_a ^ _b))
+  assert(~a === (mask & ~_a).asUInt)
+  assert((a & b) === (_a & _b).asUInt)
+  assert((a | b) === (_a | _b).asUInt)
+  assert((a ^ b) === (_a ^ _b).asUInt)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Counter.scala b/src/test/scala/chiselTests/Counter.scala
index cccd8c0e..55c07772 100644
--- a/src/test/scala/chiselTests/Counter.scala
+++ b/src/test/scala/chiselTests/Counter.scala
@@ -12,7 +12,7 @@ import chisel3.util._
 class CountTester(max: Int) extends BasicTester {
   val cnt = Counter(max)
   when(true.B) { cnt.inc() }
-  when(cnt.value === UInt(max-1)) {
+  when(cnt.value === (max-1).asUInt) {
     stop()
   }
 }
@@ -25,7 +25,7 @@ class EnableTester(seed: Int) extends BasicTester {
   val (_, done) = Counter(true.B, 33)
 
   when(done) {
-    assert(cntEnVal === UInt(popCount(seed)))
+    assert(cntEnVal === popCount(seed).asUInt)
     stop()
   }
 }
@@ -33,7 +33,7 @@ class EnableTester(seed: Int) extends BasicTester {
 class WrapTester(max: Int) extends BasicTester {
   val (cnt, wrap) = Counter(true.B, max)
   when(wrap) {
-    assert(cnt === UInt(max - 1))
+    assert(cnt === (max - 1).asUInt)
     stop()
   }
 }
diff --git a/src/test/scala/chiselTests/MulLookup.scala b/src/test/scala/chiselTests/MulLookup.scala
index f0b2aa21..936f3a45 100644
--- a/src/test/scala/chiselTests/MulLookup.scala
+++ b/src/test/scala/chiselTests/MulLookup.scala
@@ -11,13 +11,13 @@ class MulLookup(val w: Int) extends Module {
   val io = IO(new Bundle {
     val x   = Input(UInt(w.W))
     val y   = Input(UInt(w.W))
-    val z   = Output(UInt.width(2 * w))
+    val z   = Output(UInt((2 * w).W))
   })
   val tbl = Vec(
     for {
       i <- 0 until 1 << w
       j <- 0 until 1 << w
-    } yield UInt(i * j, 2 * w)
+    } yield (i * j).asUInt((2 * w).W)
   )
   io.z := tbl(((io.x << w) | io.y))
 }
@@ -26,7 +26,7 @@ class MulLookupTester(w: Int, x: Int, y: Int) extends BasicTester {
   val dut = Module(new MulLookup(w))
   dut.io.x := x.asUInt
   dut.io.y := y.asUInt
-  assert(dut.io.z === UInt(x * y))
+  assert(dut.io.z === (x * y).asUInt)
   stop()
 }
 
diff --git a/src/test/scala/chiselTests/Stack.scala b/src/test/scala/chiselTests/Stack.scala
index ce8fd9fc..58a05937 100644
--- a/src/test/scala/chiselTests/Stack.scala
+++ b/src/test/scala/chiselTests/Stack.scala
@@ -17,7 +17,7 @@ class ChiselStack(val depth: Int) extends Module {
   })
 
   val stack_mem = Mem(depth, UInt(32.W))
-  val sp        = Reg(init = UInt(0, width = log2Up(depth + 1)))
+  val sp        = Reg(init = 0.U(log2Up(depth+1).W))
   val out       = Reg(init = 0.U(32.W))
 
   when (io.en) {
diff --git a/src/test/scala/chiselTests/Tbl.scala b/src/test/scala/chiselTests/Tbl.scala
index ccfba499..03b08709 100644
--- a/src/test/scala/chiselTests/Tbl.scala
+++ b/src/test/scala/chiselTests/Tbl.scala
@@ -11,8 +11,8 @@ import chisel3.util._
 
 class Tbl(w: Int, n: Int) extends Module {
   val io = IO(new Bundle {
-    val wi  = Input(UInt.width(log2Up(n)))
-    val ri  = Input(UInt.width(log2Up(n)))
+    val wi  = Input(UInt(log2Up(n).W))
+    val ri  = Input(UInt(log2Up(n).W))
     val we  = Input(Bool())
     val  d  = Input(UInt(w.W))
     val  o  = Output(UInt(w.W))
diff --git a/src/test/scala/chiselTests/TesterDriverSpec.scala b/src/test/scala/chiselTests/TesterDriverSpec.scala
index c0d64a43..e32368e9 100644
--- a/src/test/scala/chiselTests/TesterDriverSpec.scala
+++ b/src/test/scala/chiselTests/TesterDriverSpec.scala
@@ -21,7 +21,7 @@ class FinishTester extends BasicTester {
     stop()
   }
 
-  val test_wire = Wire(init=UInt(1, test_wire_width))
+  val test_wire = Wire(init=1.U(test_wire_width.W))
 
   // though we just set test_wire to 1, the assert below will pass because
   // the finish will change its value
diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index c621c1e1..4822d892 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -19,9 +19,9 @@ class ValueTester(w: Int, values: List[Int]) extends BasicTester {
 }
 
 class TabulateTester(n: Int) extends BasicTester {
-  val v = Vec(Range(0, n).map(i => UInt(i * 2)))
-  val x = Vec(Array.tabulate(n){ i => UInt(i * 2) })
-  val u = Vec.tabulate(n)(i => UInt(i*2))
+  val v = Vec(Range(0, n).map(i => (i*2).asUInt))
+  val x = Vec(Array.tabulate(n){ i => (i*2).asUInt })
+  val u = Vec.tabulate(n)(i => (i*2).asUInt)
 
   assert(v.asUInt() === x.asUInt())
   assert(v.asUInt() === u.asUInt())
@@ -32,7 +32,7 @@ class TabulateTester(n: Int) extends BasicTester {
 
 class ShiftRegisterTester(n: Int) extends BasicTester {
   val (cnt, wrap) = Counter(true.B, n*2)
-  val shifter = Reg(Vec(n, UInt.width(log2Up(n))))
+  val shifter = Reg(Vec(n, UInt(log2Up(n).W)))
   (shifter, shifter drop 1).zipped.foreach(_ := _)
   shifter(n-1) := cnt
   when (cnt >= n.asUInt) {
-- 
cgit v1.2.3


From c270598ddb8cbfa32f8c86cc5187c89d00e6ded0 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:22:31 -0800
Subject: Remove () from as_Int

---
 .../src/main/scala/chisel3/core/package.scala      | 31 ++++++++--------------
 src/test/scala/chiselTests/Risc.scala              | 12 ++++-----
 2 files changed, 17 insertions(+), 26 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index cae64df6..3defb4f9 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -33,24 +33,16 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(x, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt(): SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(x, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(x, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
       def asSInt(width: Width): SInt = SInt.Lit(x, width)
-
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      //def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      //def asSInt(width: Int): SInt = SInt(x, Width(width))
-
     }
 
     implicit class fromBigIntToLiteral(val x: BigInt) {
@@ -69,33 +61,32 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt(): UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(x, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt(): SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(x, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(x, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
       def asSInt(width: Width): SInt = SInt.Lit(x, width)
-
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      // def asUInt(width: Int): UInt = UInt.Lit(x, Width(width))
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      // def asSInt(width: Int): SInt = SInt(x, width)
     }
 
     implicit class fromStringToLiteral(val x: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))       // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))  // scalastyle:ignore method.name
+      /** String to UInt parse with specified width, recommended style for constants.
+        */
+      def U(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
       def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
+      /** String to UInt parse with specified width, recommended style for variables.
+        */
+      def asUInt(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)
     }
 
     object fromStringToLiteral {
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 744e3631..57586c97 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -27,13 +27,13 @@ class Risc extends Module {
   val rai  = inst(15, 8)
   val rbi  = inst( 7, 0)
 
-  val ra = Mux(rai === 0.asUInt(), 0.asUInt(), file(rai))
-  val rb = Mux(rbi === 0.asUInt(), 0.asUInt(), file(rbi))
+  val ra = Mux(rai === 0.U, 0.U, file(rai))
+  val rb = Mux(rbi === 0.U, 0.U, file(rbi))
   val rc = Wire(Bits(32.W))
 
   io.valid := false.B
-  io.out   := 0.asUInt()
-  rc       := 0.asUInt()
+  io.out   := 0.U
+  rc       := 0.U
 
   when (io.isWr) {
     code(io.wrAddr) := io.wrData
@@ -45,12 +45,12 @@ class Risc extends Module {
       is(imm_op) { rc := (rai << 8) | rbi }
     }
     io.out := rc
-    when (rci === 255.asUInt()) {
+    when (rci === 255.U) {
       io.valid := true.B
     } .otherwise {
       file(rci) := rc
     }
-    pc := pc +% 1.asUInt()
+    pc := pc +% 1.U
   }
 }
 
-- 
cgit v1.2.3


From d89b54acc5a41dcc7498d97af314e58f6cd891c8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:31:23 -0800
Subject: Refactor some code

---
 .../src/main/scala/chisel3/core/package.scala      | 14 +++----
 src/main/scala/chisel3/compatibility.scala         | 47 +++++++++++-----------
 src/main/scala/chisel3/package.scala               | 32 +++++++--------
 3 files changed, 45 insertions(+), 48 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 3defb4f9..4a032523 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -76,21 +76,19 @@ package chisel3 {
     implicit class fromStringToLiteral(val x: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(parse(x), parsedWidth(x))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(parse(x), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(fromStringToLiteral.parse(x), fromStringToLiteral.parsedWidth(x))
+      def asUInt: UInt = UInt.Lit(parse(x), parsedWidth(x))
       /** String to UInt parse with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(fromStringToLiteral.parse(x), width)
-    }
+      def asUInt(width: Width): UInt = UInt.Lit(parse(x), width)
 
-    object fromStringToLiteral {
-      def parse(n: String) = {
+      protected def parse(n: String) = {
         val (base, num) = n.splitAt(1)
         val radix = base match {
           case "x" | "h" => 16
@@ -102,7 +100,7 @@ package chisel3 {
         BigInt(num.filterNot(_ == '_'), radix)
       }
 
-      def parsedWidth(n: String) =
+      protected def parsedWidth(n: String) =
         if (n(0) == 'b') {
           Width(n.length-1)
         } else if (n(0) == 'h') {
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 625628dd..fbe37f50 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -45,29 +45,28 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        chisel3.core.fromStringToLiteral.parsedWidth(n))
+    def apply(n: String): UInt = n.asUInt
     /** Create a UInt literal with fixed width. */
-    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        Width(width))
+    def apply(n: String, width: Int): UInt = n.asUInt(width.W)
 
     /** Create a UInt literal with specified width. */
-    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): UInt = value.asUInt(width)
 
     /** Create a UInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+    def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W)
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
     // NOTE: This resolves UInt(width = 32)
-    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
-    def apply(value: BigInt): UInt = apply(value, Width())
+    def apply(value: BigInt): UInt = value.asUInt
+
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): UInt = apply(dir, Width(width))
+    def apply(dir: Direction, width: Int): UInt = apply(dir, width.W)
     /** Create a UInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): UInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): UInt = {
-      val result = apply(wWidth)
+    def apply(dir: Direction, width: Width): UInt = {
+      val result = apply(width)
       dir match {
         case chisel3.core.Direction.Input => chisel3.core.Input(result)
         case chisel3.core.Direction.Output => chisel3.core.Output(result)
@@ -76,7 +75,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     }
 
     /** Create a UInt with a specified width */
-    def width(width: Int): UInt = apply(Width(width))
+    def width(width: Int): UInt = apply(width.W)
 
     /** Create a UInt port with specified width. */
     def width(width: Width): UInt = apply(width)
@@ -86,29 +85,29 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
-    def width(width: Int): SInt = apply(Width(width))
+    def width(width: Int): SInt = apply(width.W)
     /** Create an SInt type with specified width. */
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    def apply(value: BigInt): SInt = Lit(value)
+    def apply(value: BigInt): SInt = value.S
     /** Create an SInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Int): SInt = value.S(width.W)
 
     /** Create an SInt literal with specified width. */
-    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): SInt = value.S(width)
 
-    def Lit(value: BigInt): SInt = Lit(value, Width())
-    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+    def Lit(value: BigInt): SInt = value.S
+    def Lit(value: BigInt, width: Int): SInt = value.S(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
-    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
     /** Create a SInt with a specified direction and width - compatibility with Chisel2. */
-    def apply(dir: Direction, width: Int): SInt = apply(dir, Width(width))
+    def apply(dir: Direction, width: Int): SInt = apply(dir, width.W)
     /** Create a SInt with a specified direction, but unspecified width - compatibility with Chisel2. */
     def apply(dir: Direction): SInt = apply(dir, Width())
-    def apply(dir: Direction, wWidth: Width): SInt = {
-      val result = apply(wWidth)
+    def apply(dir: Direction, width: Width): SInt = {
+      val result = apply(width)
       dir match {
         case chisel3.core.Direction.Input => chisel3.core.Input(result)
         case chisel3.core.Direction.Output => chisel3.core.Output(result)
@@ -122,7 +121,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
      */
-    def apply(x: Boolean): Bool = Lit(x)
+    def apply(x: Boolean): Bool = x.B
 
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
     def apply(dir: Direction): Bool = {
@@ -175,6 +174,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val Driver = chisel3.Driver
   val ImplicitConversions = chisel3.util.ImplicitConversions
 
+  // Deprecated as of Chisel3
   object chiselMain {
     import java.io.File
 
@@ -194,6 +194,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def apply (arg: Data): Data = arg
   }
 
+  // Deprecated as of Chsiel3
   @throws(classOf[Exception])
   object throwException {
     def apply(s: String, t: Throwable = null) = {
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 5b02be34..326f8d7c 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -33,7 +33,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Bits = chisel3.core.Bits
 
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
-    * These will be removed very soon. It's recommended you move your code soon.
+    * These will be removed very soon. It's recommended you port your code ASAP.
     *
     * Some recommended regex replacements:
     * (note: these are not guaranteed to handle all edge cases! check all replacements!)
@@ -48,32 +48,30 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
     @deprecated("use n.U", "chisel3, will be removed by end of 2016")
-    def apply(n: String): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        chisel3.core.fromStringToLiteral.parsedWidth(n))
+    def apply(n: String): UInt = n.asUInt
     /** Create a UInt literal with fixed width. */
     @deprecated("use n.U(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(n: String, width: Int): UInt = Lit(chisel3.core.fromStringToLiteral.parse(n),
-        Width(width))
+    def apply(n: String, width: Int): UInt = n.asUInt(width.W)
 
     /** Create a UInt literal with specified width. */
     @deprecated("use value.U(width)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Width): UInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): UInt = value.asUInt(width)
 
     /** Create a UInt literal with fixed width. */
     @deprecated("use value.U(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Int): UInt = Lit(value, Width(width))
+    def apply(value: BigInt, width: Int): UInt = value.asUInt(width.W)
 
     /** Create a UInt with a specified width - compatibility with Chisel2. */
     @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(Width(width))
+    def apply(dir: Option[Direction] = None, width: Int): UInt = apply(width.W)
 
     /** Create a UInt literal with inferred width.- compatibility with Chisel2. */
     @deprecated("use value.U", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt): UInt = apply(value, Width())
+    def apply(value: BigInt): UInt = value.asUInt
 
     /** Create a UInt with a specified width */
     @deprecated("use UInt(width.W)", "chisel3, will be removed by end of 2016")
-    def width(width: Int): UInt = apply(Width(width))
+    def width(width: Int): UInt = apply(width.W)
 
     /** Create a UInt port with specified width. */
     @deprecated("use UInt(width)", "chisel3, will be removed by end of 2016")
@@ -86,27 +84,27 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   trait SIntFactory extends chisel3.core.SIntFactory {
     /** Create a SInt type or port with fixed width. */
     @deprecated("use SInt(width.W)", "chisel3, will be removed by end of 2016")
-    def width(width: Int): SInt = apply(Width(width))
+    def width(width: Int): SInt = apply(width.W)
     /** Create an SInt type with specified width. */
     @deprecated("use SInt(width)", "chisel3, will be removed by end of 2016")
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
     @deprecated("use value.S", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt): SInt = Lit(value)
+    def apply(value: BigInt): SInt = value.asSInt
     /** Create an SInt literal with fixed width. */
     @deprecated("use value.S(width.W)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Int): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create an SInt literal with specified width. */
     @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
-    def apply(value: BigInt, width: Width): SInt = Lit(value, width)
+    def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
     @deprecated("use value.S", "chisel3, will be removed by end of 2016")
-    def Lit(value: BigInt): SInt = Lit(value, Width())
+    def Lit(value: BigInt): SInt = value.asSInt
 
     @deprecated("use value.S(width)", "chisel3, will be removed by end of 2016")
-    def Lit(value: BigInt, width: Int): SInt = Lit(value, Width(width))
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
   }
 
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
@@ -116,7 +114,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     /** Creates Bool literal.
      */
     @deprecated("use x.B", "chisel3, will be removed by end of 2016")
-    def apply(x: Boolean): Bool = Lit(x)
+    def apply(x: Boolean): Bool = x.B
   }
 
   object Bits extends UIntFactory
-- 
cgit v1.2.3


From a2b97f8dc9c261ae4dc39ea4e11feed7723e22dd Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:36:16 -0800
Subject: Restyle UInt->BitPatComparable

---
 src/main/scala/chisel3/package.scala | 12 ++++++++----
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 326f8d7c..7b07d964 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,10 +1,8 @@
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
-  import scala.language.experimental.macros
+  import internal.firrtl.Width
 
-  import internal.firrtl.{Width, NumericBound}
-  import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
   import util.BitPat
 
   import chisel3.core.{Binding, FlippedBinder}
@@ -206,7 +204,10 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
   implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
 
-  implicit class fromUIntToBitPatComparable(val x: UInt) extends AnyVal {
+  implicit class fromUIntToBitPatComparable(val x: UInt) {
+    import scala.language.experimental.macros
+    import internal.sourceinfo.{SourceInfo, SourceInfoTransform}
+
     final def === (that: BitPat): Bool = macro SourceInfoTransform.thatArg
     @deprecated("Use '=/=', which avoids potential precedence problems", "chisel3")
     final def != (that: BitPat): Bool = macro SourceInfoTransform.thatArg
@@ -254,6 +255,9 @@ package object chisel3 {    // scalastyle:ignore package.object.name
     implicit def fromStringToStringParam(x: String): StringParam = StringParam(x)
 
     implicit class ChiselRange(val sc: StringContext) extends AnyVal {
+      import scala.language.experimental.macros
+      import internal.firrtl.NumericBound
+
       /** Specifies a range using mathematical range notation. Variables can be interpolated using
        *  standard string interpolation syntax.
         * @example {{{
-- 
cgit v1.2.3


From ebe7a0fb5774ec4bec919f9d3acd987d084d91b4 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 13:50:50 -0800
Subject: better style

---
 chiselFrontend/src/main/scala/chisel3/core/package.scala |  2 +-
 src/main/scala/chisel3/compatibility.scala               | 10 +++++-----
 src/main/scala/chisel3/util/ImplicitConversions.scala    |  2 ++
 3 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 4a032523..7c11d446 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -128,4 +128,4 @@ package chisel3 {
       def W: Width = Width(x)  // scalastyle:ignore method.name
     }
   }
-}
\ No newline at end of file
+}
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index fbe37f50..ff627c1e 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -90,15 +90,15 @@ package object Chisel {     // scalastyle:ignore package.object.name
     def width(width: Width): SInt = apply(width)
 
     /** Create an SInt literal with inferred width. */
-    def apply(value: BigInt): SInt = value.S
+    def apply(value: BigInt): SInt = value.asSInt
     /** Create an SInt literal with fixed width. */
-    def apply(value: BigInt, width: Int): SInt = value.S(width.W)
+    def apply(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create an SInt literal with specified width. */
-    def apply(value: BigInt, width: Width): SInt = value.S(width)
+    def apply(value: BigInt, width: Width): SInt = value.asSInt(width)
 
-    def Lit(value: BigInt): SInt = value.S
-    def Lit(value: BigInt, width: Int): SInt = value.S(width.W)
+    def Lit(value: BigInt): SInt = value.asSInt
+    def Lit(value: BigInt, width: Int): SInt = value.asSInt(width.W)
 
     /** Create a SInt with a specified width - compatibility with Chisel2. */
     def apply(dir: Option[Direction] = None, width: Int): SInt = apply(width.W)
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index 7f715ad4..c2ba710d 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -5,6 +5,8 @@ package chisel3.util
 import chisel3._
 
 object ImplicitConversions {
+  // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
+  // UInt.asUInt.
   implicit def intToUInt(x: Int): UInt = chisel3.core.fromIntToLiteral(x).asUInt
   implicit def booleanToBool(x: Boolean): Bool = x.asBool
 }
-- 
cgit v1.2.3


From b50dbf2e17053d601213855642c117f429204fb8 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 14:40:31 -0800
Subject: Stop confusing scaladoc

---
 src/main/scala/chisel3/package.scala | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 7b07d964..50cb3dbe 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -30,18 +30,25 @@ package object chisel3 {    // scalastyle:ignore package.object.name
   type Element = chisel3.core.Element
   type Bits = chisel3.core.Bits
 
+  // Some possible regex replacements for the literal specifier deprecation:
+  // (note: these are not guaranteed to handle all edge cases! check all replacements!)
+  // Bool((true|false))
+  //  => $1.B
+  // UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => UInt($1.W)
+  // (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $1($2.W)
+  // (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\)
+  //  => $2.$1
+  // UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $1.U($2.W)
+  // (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $2.as$1
+  // (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
+  //  => $2.as$1($3.W)
+
   /** This contains literal constructor factory methods that are deprecated as of Chisel3.
     * These will be removed very soon. It's recommended you port your code ASAP.
-    *
-    * Some recommended regex replacements:
-    * (note: these are not guaranteed to handle all edge cases! check all replacements!)
-    * Bool((true|false)) => $1.B
-    * UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => UInt($1.W)
-    * (UInt|SInt|Bits).width\((\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1($2.W)
-    * (U|S)Int\((-?\d+|0[xX][0-9a-fA-F]+)\) => $2.$1
-    * UInt\((\d+|0[xX][0-9a-fA-F]+),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $1.U($2.W)
-    * (UInt|SInt|Bool)\(([_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1
-    * (UInt|SInt)\(([_a-zA-Z][_0-9a-zA-Z]*),\s*(?:width\s*=)?\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\) => $2.as$1($3.W)
     */
   trait UIntFactory extends chisel3.core.UIntFactory {
     /** Create a UInt literal with inferred width. */
-- 
cgit v1.2.3


From 75da1093142b57a58d61fe5e57181041bc59146d Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 17 Nov 2016 15:37:20 -0800
Subject: Fix regex example

---
 src/main/scala/chisel3/package.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 50cb3dbe..44d1f6c1 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -32,7 +32,7 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   // Some possible regex replacements for the literal specifier deprecation:
   // (note: these are not guaranteed to handle all edge cases! check all replacements!)
-  // Bool((true|false))
+  // Bool\((true|false)\)
   //  => $1.B
   // UInt\(width\s*=\s*(\d+|[_a-zA-Z][_0-9a-zA-Z]*)\)
   //  => UInt($1.W)
-- 
cgit v1.2.3


From 6b7acc715010b14c22e15f5084efb11862151a47 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 12:50:35 -0800
Subject: Fix Log2

---
 src/main/scala/chisel3/util/CircuitMath.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/chisel3/util/CircuitMath.scala b/src/main/scala/chisel3/util/CircuitMath.scala
index 83e5feb1..a422b5fe 100644
--- a/src/main/scala/chisel3/util/CircuitMath.scala
+++ b/src/main/scala/chisel3/util/CircuitMath.scala
@@ -18,7 +18,7 @@ object Log2 {
     } else if (width == 2) {
       x(1)
     } else if (width <= divideAndConquerThreshold) {
-      Mux(x(width-1), UInt((width-1).W), apply(x, width-1))
+      Mux(x(width-1), (width-1).asUInt, apply(x, width-1))
     } else {
       val mid = 1 << (log2Ceil(width) - 1)
       val hi = x(width-1, mid)
-- 
cgit v1.2.3


From 70161db5b6ae88b4ba1edfd8032e6ed381734dab Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:15:46 -0800
Subject: Convert rest of tests

---
 src/test/scala/chiselTests/BlackBox.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 8b4cf157..7fcba766 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -89,25 +89,25 @@ class BlackBoxConstant(value: Int) extends BlackBox(
     Map("VALUE" -> value, "WIDTH" -> log2Up(value + 1))) {
   require(value >= 0, "value must be a UInt!")
   val io = IO(new Bundle {
-    val out = UInt(width = log2Up(value + 1)).asOutput
+    val out = UInt(log2Up(value + 1).W).asOutput
   })
 }
 
 class BlackBoxStringParam(str: String) extends BlackBox(Map("STRING" -> str)) {
   val io = IO(new Bundle {
-    val out = UInt(width = 32)
+    val out = UInt(32.W)
   })
 }
 
 class BlackBoxRealParam(dbl: Double) extends BlackBox(Map("REAL" -> dbl)) {
   val io = IO(new Bundle {
-    val out = UInt(width = 64)
+    val out = UInt(64.W)
   })
 }
 
 class BlackBoxTypeParam(w: Int, raw: String) extends BlackBox(Map("T" -> RawParam(raw))) {
   val io = IO(new Bundle {
-    val out = UInt(width = w)
+    val out = UInt(w.W)
   })
 }
 
@@ -127,7 +127,7 @@ class BlackBoxWithParamsTester extends BasicTester {
   assert(blackBoxFour.io.out === 4.U)
   assert(blackBoxStringParamOne.io.out === 1.U)
   assert(blackBoxStringParamTwo.io.out === 2.U)
-  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
+  assert(blackBoxRealParamOne.io.out === BigInt(0x3ff0000000000000L).U)
   assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
   assert(blackBoxTypeParamBit.io.out === 1.U)
   assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
-- 
cgit v1.2.3


From 81e5d00d18a5ba9ae33c10219a270148002fc672 Mon Sep 17 00:00:00 2001
From: ducky
Date: Fri, 18 Nov 2016 13:36:03 -0800
Subject: Deboilerplate the implicit conversions, add support for long.U

---
 .../src/main/scala/chisel3/core/package.scala      | 71 +++++++---------------
 src/main/scala/chisel3/compatibility.scala         | 11 ++--
 src/main/scala/chisel3/package.scala               | 13 ++--
 src/test/scala/chiselTests/BlackBox.scala          |  2 +-
 4 files changed, 37 insertions(+), 60 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 7c11d446..77f35c23 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -17,76 +17,51 @@ package chisel3 {
     * confusion (the 1 is a bit length and the 0 is a bit extraction position).
     * Prefer storing the result and then extracting from it.
     */
-    implicit class fromIntToLiteral(val x: Int) {
+    implicit class fromBigIntToLiteral(val bigint: BigInt) {
       /** Int to UInt conversion, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to SInt conversion, recommended style for constants.
         */
-      def S: SInt = SInt.Lit(BigInt(x), Width())  // scalastyle:ignore method.name
+      def S: SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to UInt conversion with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(bigint, width)  // scalastyle:ignore method.name
       /** Int to SInt conversion with specified width, recommended style for constants.
         */
-      def S(width: Width): SInt = SInt.Lit(BigInt(x), width)  // scalastyle:ignore method.name
+      def S(width: Width): SInt = SInt.Lit(bigint, width)  // scalastyle:ignore method.name
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(x, Width())
+      def asUInt: UInt = UInt.Lit(bigint, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt: SInt = SInt.Lit(x, Width())
+      def asSInt: SInt = SInt.Lit(bigint, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(x, width)
+      def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
       /** Int to SInt conversion with specified width, recommended style for variables.
         */
-      def asSInt(width: Width): SInt = SInt.Lit(x, width)
+      def asSInt(width: Width): SInt = SInt.Lit(bigint, width)
     }
 
-    implicit class fromBigIntToLiteral(val x: BigInt) {
-      /** Int to UInt conversion, recommended style for constants.
-        */
-      def U: UInt = UInt.Lit(x, Width())  // scalastyle:ignore method.name
-      /** Int to SInt conversion, recommended style for constants.
-        */
-      def S: SInt = SInt.Lit(x, Width())  // scalastyle:ignore method.name
-      /** Int to UInt conversion with specified width, recommended style for constants.
-        */
-      def U(width: Width): UInt = UInt.Lit(x, width)  // scalastyle:ignore method.name
-      /** Int to SInt conversion with specified width, recommended style for constants.
-        */
-      def S(width: Width): SInt = SInt.Lit(x, width)  // scalastyle:ignore method.name
-
-      /** Int to UInt conversion, recommended style for variables.
-        */
-      def asUInt: UInt = UInt.Lit(x, Width())
-      /** Int to SInt conversion, recommended style for variables.
-        */
-      def asSInt: SInt = SInt.Lit(x, Width())
-      /** Int to UInt conversion with specified width, recommended style for variables.
-        */
-      def asUInt(width: Width): UInt = UInt.Lit(x, width)
-      /** Int to SInt conversion with specified width, recommended style for variables.
-        */
-      def asSInt(width: Width): SInt = SInt.Lit(x, width)
-    }
+    implicit class fromIntToLiteral(val int: Int) extends fromBigIntToLiteral(int)
+    implicit class fromLongToLiteral(val long: Long) extends fromBigIntToLiteral(long)
 
-    implicit class fromStringToLiteral(val x: String) {
+    implicit class fromStringToLiteral(val str: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(parse(x), parsedWidth(x))  // scalastyle:ignore method.name
+      def U: UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
-      def U(width: Width): UInt = UInt.Lit(parse(x), width)  // scalastyle:ignore method.name
+      def U(width: Width): UInt = UInt.Lit(parse(str), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(parse(x), parsedWidth(x))
+      def asUInt: UInt = UInt.Lit(parse(str), parsedWidth(str))
       /** String to UInt parse with specified width, recommended style for variables.
         */
-      def asUInt(width: Width): UInt = UInt.Lit(parse(x), width)
+      def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
 
       protected def parse(n: String) = {
         val (base, num) = n.splitAt(1)
@@ -110,22 +85,22 @@ package chisel3 {
         }
     }
 
-    implicit class fromBooleanToLiteral(val x: Boolean) {
+    implicit class fromBooleanToLiteral(val boolean: Boolean) {
       /** Boolean to Bool conversion, recommended style for constants.
         */
-      def B: Bool = Bool.Lit(x)  // scalastyle:ignore method.name
+      def B: Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
 
       /** Boolean to Bool conversion, recommended style for variables.
         */
-      def asBool: Bool = Bool.Lit(x)
+      def asBool: Bool = Bool.Lit(boolean)
     }
 
-    implicit class fromDoubleToLiteral(val x: Double) {
-      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(x, binaryPoint = binaryPoint)
+    implicit class fromDoubleToLiteral(val double: Double) {
+      def F(binaryPoint: Int): FixedPoint = FixedPoint.fromDouble(double, binaryPoint = binaryPoint)
     }
 
-    implicit class fromIntToWidth(val x: Int) {
-      def W: Width = Width(x)  // scalastyle:ignore method.name
+    implicit class fromIntToWidth(val int: Int) {
+      def W: Width = Width(int)  // scalastyle:ignore method.name
     }
   }
 }
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index ff627c1e..51176d9d 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -164,11 +164,12 @@ package object Chisel {     // scalastyle:ignore package.object.name
   val when = chisel3.core.when
   type WhenContext = chisel3.core.WhenContext
 
-  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
-  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
-  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
-  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
-  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
+  implicit class fromBigIntToLiteral(val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromtIntToLiteral(val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromtLongToLiteral(val x: Long) extends chisel3.core.fromLongToLiteral(x)
+  implicit class fromStringToLiteral(val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromIntToWidth(val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   type BackendCompilationUtilities = chisel3.BackendCompilationUtilities
   val Driver = chisel3.Driver
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 44d1f6c1..449f4ea5 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -204,12 +204,13 @@ package object chisel3 {    // scalastyle:ignore package.object.name
 
   implicit def string2Printable(str: String): Printable = PString(str)
 
-  implicit class fromtIntToLiteral(override val x: Int) extends chisel3.core.fromIntToLiteral(x)
-  implicit class fromBigIntToLiteral(override val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
-  implicit class fromStringToLiteral(override val x: String) extends chisel3.core.fromStringToLiteral(x)
-  implicit class fromBooleanToLiteral(override val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
-  implicit class fromDoubleToLiteral(override val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
-  implicit class fromIntToWidth(override val x: Int) extends chisel3.core.fromIntToWidth(x)
+  implicit class fromBigIntToLiteral(val x: BigInt) extends chisel3.core.fromBigIntToLiteral(x)
+  implicit class fromtIntToLiteral(val x: Int) extends chisel3.core.fromIntToLiteral(x)
+  implicit class fromtLongToLiteral(val x: Long) extends chisel3.core.fromLongToLiteral(x)
+  implicit class fromStringToLiteral(val x: String) extends chisel3.core.fromStringToLiteral(x)
+  implicit class fromBooleanToLiteral(val x: Boolean) extends chisel3.core.fromBooleanToLiteral(x)
+  implicit class fromDoubleToLiteral(val x: Double) extends chisel3.core.fromDoubleToLiteral(x)
+  implicit class fromIntToWidth(val x: Int) extends chisel3.core.fromIntToWidth(x)
 
   implicit class fromUIntToBitPatComparable(val x: UInt) {
     import scala.language.experimental.macros
diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala
index 7fcba766..d42cd791 100644
--- a/src/test/scala/chiselTests/BlackBox.scala
+++ b/src/test/scala/chiselTests/BlackBox.scala
@@ -127,7 +127,7 @@ class BlackBoxWithParamsTester extends BasicTester {
   assert(blackBoxFour.io.out === 4.U)
   assert(blackBoxStringParamOne.io.out === 1.U)
   assert(blackBoxStringParamTwo.io.out === 2.U)
-  assert(blackBoxRealParamOne.io.out === BigInt(0x3ff0000000000000L).U)
+  assert(blackBoxRealParamOne.io.out === 0x3ff0000000000000L.U)
   assert(blackBoxRealParamNeg.io.out === BigInt("bff0000000000000", 16).U)
   assert(blackBoxTypeParamBit.io.out === 1.U)
   assert(blackBoxTypeParamWord.io.out === "hdeadbeef".U(32.W))
-- 
cgit v1.2.3


From 11302f77c90512f81b882ad1cc623c53d45724f8 Mon Sep 17 00:00:00 2001
From: Donggyu
Date: Mon, 21 Nov 2016 14:52:05 -0800
Subject: Remove deduplication from Chisel (#347)

Remove modName from Module---
 .../src/main/scala/chisel3/core/Module.scala         |  9 ---------
 .../src/main/scala/chisel3/internal/Builder.scala    |  2 +-
 src/main/scala/chisel3/internal/firrtl/Emitter.scala | 20 +++++---------------
 3 files changed, 6 insertions(+), 25 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Module.scala b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
index 62b6d5ce..bd406529 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Module.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Module.scala
@@ -124,18 +124,9 @@ extends HasId {
   /** Legalized name of this module. */
   final val name = Builder.globalNamespace.name(desiredName)
 
-  /** FIRRTL Module name */
-  private var _modName: Option[String] = None
-  private[chisel3] def setModName(name: String) = _modName = Some(name)
-  def modName = _modName match {
-    case Some(name) => name
-    case None => throwException("modName should be called after circuit elaboration")
-  }
-
   /** Keep component for signal names */
   private[chisel3] var _component: Option[Component] = None
 
-
   /** Signal name (for simulation). */
   override def instanceName =
     if (_parent == None) name else _component match {
diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
index 60ce6d5d..cf86b0e7 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala
@@ -124,7 +124,7 @@ private[chisel3] trait HasId extends InstanceId {
     case None => throwException(s"$instanceName doesn't have a parent")
   }
   def parentModName = _parent match {
-    case Some(p) => p.modName
+    case Some(p) => p.name
     case None => throwException(s"$instanceName doesn't have a parent")
   }
 
diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
index b8651828..42bc6c30 100644
--- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala
+++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala
@@ -32,7 +32,7 @@ private class Emitter(circuit: Circuit) {
           "\"" + printf.format(fmt) + "\"") ++ args
         printfArgs mkString ("printf(", ", ", ")")
       case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid"
-      case e: DefInstance => s"inst ${e.name} of ${e.id.modName}"
+      case e: DefInstance => s"inst ${e.name} of ${e.id.name}"
       case w: WhenBegin =>
         indent()
         s"when ${w.pred.fullName(ctx)} :"
@@ -53,9 +53,6 @@ private class Emitter(circuit: Circuit) {
     s"parameter $name = $str"
   }
 
-  // Map of Module FIRRTL definition to FIRRTL name, if it has been emitted already.
-  private val defnMap = collection.mutable.HashMap[(String, String), Component]()
-
   /** Generates the FIRRTL module declaration.
     */
   private def moduleDecl(m: Component): String = m.id match {
@@ -92,17 +89,10 @@ private class Emitter(circuit: Circuit) {
     */
   private def emit(m: Component): String = {
     // Generate the body.
-    val defn = moduleDefn(m)
-
-    defnMap get (m.id.desiredName, defn) match {
-      case Some(duplicate) =>
-        m.id setModName duplicate.name
-        ""
-      case None =>
-        defnMap((m.id.desiredName, defn)) = m
-        m.id setModName m.name
-        moduleDecl(m) + defn
-    }
+    val sb = new StringBuilder
+    sb.append(moduleDecl(m))
+    sb.append(moduleDefn(m))
+    sb.result
   }
 
   private var indentLevel = 0
-- 
cgit v1.2.3


From 3c31b9af6b1dc9abde701edb33d4be36c192bad2 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Mon, 21 Nov 2016 17:18:26 -0800
Subject: Fix toBits() deprecation message (to match what it effectively does).
 (#379)

Data.toUInt() doesn't exist.---
 chiselFrontend/src/main/scala/chisel3/core/Data.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Data.scala b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
index 2f18e726..57ed0c59 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Data.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Data.scala
@@ -258,7 +258,7 @@ abstract class Data extends HasId {
     *
     * This performs the inverse operation of fromBits(Bits).
     */
-  @deprecated("Best alternative, .toUInt() or if Bits really needed, .toUInt().toBits()", "chisel3")
+  @deprecated("Best alternative, .asUInt()", "chisel3")
   def toBits(): UInt = SeqUtils.do_asUInt(this.flatten)(DeprecatedSourceInfo)
 
   /** Reinterpret cast to UInt.
-- 
cgit v1.2.3


From 8cb4e0cc38e2bf1ec596ae000caaf8e49c47dc31 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 22 Nov 2016 00:57:12 -0800
Subject: Disallow chained apply (#380)

---
 .../src/main/scala/chisel3/core/Aggregate.scala      |  2 +-
 .../src/main/scala/chisel3/core/Bits.scala           |  4 ++--
 .../src/main/scala/chisel3/core/package.scala        | 20 ++++++++++++--------
 3 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 8fdcb260..17354799 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -126,7 +126,7 @@ object Vec {
     if (n <= 1) 0.U
     else if (idx.width.known && idx.width.get <= w) idx
     else if (idx.width.known) idx(w-1,0)
-    else (idx | 0.U(w))(w-1,0)
+    else (idx | 0.U(w.W))(w-1,0)
   }
 }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index 354512e1..cab1a82e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -478,7 +478,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
 
   final def unary_! () : Bool = macro SourceInfoTransform.noArg
 
-  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1)
+  def do_unary_! (implicit sourceInfo: SourceInfo) : Bool = this === 0.U(1.W)
 
   override def do_<< (that: Int)(implicit sourceInfo: SourceInfo): UInt =
     binop(sourceInfo, UInt(this.width + that), ShiftLeftOp, that)
@@ -496,7 +496,7 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
   final def bitSet(off: UInt, dat: Bool): UInt = macro UIntTransform.bitset
 
   def do_bitSet(off: UInt, dat: Bool)(implicit sourceInfo: SourceInfo): UInt = {
-    val bit = 1.U(1) << off
+    val bit = 1.U(1.W) << off
     Mux(dat, this | bit, ~(~this | bit))
   }
 
diff --git a/chiselFrontend/src/main/scala/chisel3/core/package.scala b/chiselFrontend/src/main/scala/chisel3/core/package.scala
index 77f35c23..1d5817ae 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/package.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/package.scala
@@ -16,14 +16,18 @@ package chisel3 {
     * after this call using apply, ie. 0.asUInt(1)(0) due to potential for
     * confusion (the 1 is a bit length and the 0 is a bit extraction position).
     * Prefer storing the result and then extracting from it.
+    *
+    * Implementation note: the empty parameter list (like `U()`) is necessary to prevent
+    * interpreting calls that have a non-Width parameter as a chained apply, otherwise things like
+    * `0.asUInt(16)` (instead of `16.W`) compile without error and produce undesired results.
     */
     implicit class fromBigIntToLiteral(val bigint: BigInt) {
       /** Int to UInt conversion, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
+      def U(): UInt = UInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to SInt conversion, recommended style for constants.
         */
-      def S: SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
+      def S(): SInt = SInt.Lit(bigint, Width())  // scalastyle:ignore method.name
       /** Int to UInt conversion with specified width, recommended style for constants.
         */
       def U(width: Width): UInt = UInt.Lit(bigint, width)  // scalastyle:ignore method.name
@@ -33,10 +37,10 @@ package chisel3 {
 
       /** Int to UInt conversion, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(bigint, Width())
+      def asUInt(): UInt = UInt.Lit(bigint, Width())
       /** Int to SInt conversion, recommended style for variables.
         */
-      def asSInt: SInt = SInt.Lit(bigint, Width())
+      def asSInt(): SInt = SInt.Lit(bigint, Width())
       /** Int to UInt conversion with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(bigint, width)
@@ -51,14 +55,14 @@ package chisel3 {
     implicit class fromStringToLiteral(val str: String) {
       /** String to UInt parse, recommended style for constants.
         */
-      def U: UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
+      def U(): UInt = UInt.Lit(parse(str), parsedWidth(str))  // scalastyle:ignore method.name
       /** String to UInt parse with specified width, recommended style for constants.
         */
       def U(width: Width): UInt = UInt.Lit(parse(str), width)  // scalastyle:ignore method.name
 
       /** String to UInt parse, recommended style for variables.
         */
-      def asUInt: UInt = UInt.Lit(parse(str), parsedWidth(str))
+      def asUInt(): UInt = UInt.Lit(parse(str), parsedWidth(str))
       /** String to UInt parse with specified width, recommended style for variables.
         */
       def asUInt(width: Width): UInt = UInt.Lit(parse(str), width)
@@ -88,11 +92,11 @@ package chisel3 {
     implicit class fromBooleanToLiteral(val boolean: Boolean) {
       /** Boolean to Bool conversion, recommended style for constants.
         */
-      def B: Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
+      def B(): Bool = Bool.Lit(boolean)  // scalastyle:ignore method.name
 
       /** Boolean to Bool conversion, recommended style for variables.
         */
-      def asBool: Bool = Bool.Lit(boolean)
+      def asBool(): Bool = Bool.Lit(boolean)
     }
 
     implicit class fromDoubleToLiteral(val double: Double) {
-- 
cgit v1.2.3


From aadab5ae2c957f9619e8d8c5a2518a871eea2659 Mon Sep 17 00:00:00 2001
From: ducky
Date: Mon, 21 Nov 2016 16:46:39 -0800
Subject: Don't publish sub-project JARs

---
 build.sbt | 14 ++++++++------
 1 file changed, 8 insertions(+), 6 deletions(-)

diff --git a/build.sbt b/build.sbt
index dd36f25f..939865d9 100644
--- a/build.sbt
+++ b/build.sbt
@@ -98,16 +98,19 @@ lazy val chiselSettings = Seq (
 lazy val coreMacros = (project in file("coreMacros")).
   settings(commonSettings: _*).
   settings(
-    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value
+    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+    publishArtifact := false
   )
 
 lazy val chiselFrontend = (project in file("chiselFrontend")).
   settings(commonSettings: _*).
   settings(
-    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value
+    libraryDependencies += "org.scala-lang" % "scala-reflect" % scalaVersion.value,
+    publishArtifact := false
   ).
   dependsOn(coreMacros)
 
+
 lazy val chisel = (project in file(".")).
   enablePlugins(BuildInfoPlugin).
   settings(
@@ -119,8 +122,8 @@ lazy val chisel = (project in file(".")).
   settings(commonSettings: _*).
   settings(customUnidocSettings: _*).
   settings(chiselSettings: _*).
-  dependsOn(coreMacros).
-  dependsOn(chiselFrontend).
+  dependsOn(coreMacros % "compile-internal;test-internal").
+  dependsOn(chiselFrontend % "compile-internal;test-internal").
   settings(
     aggregate in doc := false,
     // Include macro classes, resources, and sources main jar.
@@ -128,5 +131,4 @@ lazy val chisel = (project in file(".")).
     mappings in (Compile, packageSrc) <++= mappings in (coreMacros, Compile, packageSrc),
     mappings in (Compile, packageBin) <++= mappings in (chiselFrontend, Compile, packageBin),
     mappings in (Compile, packageSrc) <++= mappings in (chiselFrontend, Compile, packageSrc)
-  ).
-  aggregate(coreMacros, chiselFrontend)
+  )
-- 
cgit v1.2.3


From 93dd0ed20858ad8e8ebfd73f283f98b4508be32a Mon Sep 17 00:00:00 2001
From: ducky
Date: Wed, 23 Nov 2016 13:49:24 -0800
Subject: Fix for direct dependencies

---
 build.sbt | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/build.sbt b/build.sbt
index 939865d9..ba629250 100644
--- a/build.sbt
+++ b/build.sbt
@@ -122,13 +122,17 @@ lazy val chisel = (project in file(".")).
   settings(commonSettings: _*).
   settings(customUnidocSettings: _*).
   settings(chiselSettings: _*).
+  // Prevent separate JARs from being generated for coreMacros and chiselFrontend.
   dependsOn(coreMacros % "compile-internal;test-internal").
   dependsOn(chiselFrontend % "compile-internal;test-internal").
   settings(
     aggregate in doc := false,
-    // Include macro classes, resources, and sources main jar.
+    // Include macro classes, resources, and sources main JAR.
     mappings in (Compile, packageBin) <++= mappings in (coreMacros, Compile, packageBin),
     mappings in (Compile, packageSrc) <++= mappings in (coreMacros, Compile, packageSrc),
     mappings in (Compile, packageBin) <++= mappings in (chiselFrontend, Compile, packageBin),
-    mappings in (Compile, packageSrc) <++= mappings in (chiselFrontend, Compile, packageSrc)
+    mappings in (Compile, packageSrc) <++= mappings in (chiselFrontend, Compile, packageSrc),
+    // Export the packaged JAR so projects that depend directly on Chisel project (rather than the
+    // published artifact) also see the stuff in coreMacros and chiselFrontend.
+    exportJars := true
   )
-- 
cgit v1.2.3


From edb19a0559686a471141c74438f677c1e217a298 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Wed, 23 Nov 2016 16:01:50 -0800
Subject: Simplify Enum API (#385)

Get rid of some cruft exposed in #373

This also allows Bits.fromtInt(...) to be removed. Yay!

All old APIs (with some new restrictions, rocket still works fine) are preserved without deprecation in Chisel._, aside from the non-compile-time-checkable Map[] enum constructor which probably should have been deprecated during chisel2. The Map[] enums have been removed from chisel3._ without deprecation.

The new restriction is that nodeType (legacy API) may only be of UInt type with unspecified width. Note that Bits() creates a UInt, and if you can't control the enum values, it makes little sense to specify a bitwidth.---
 .../src/main/scala/chisel3/core/Bits.scala         | 17 -------
 src/main/scala/chisel3/compatibility.scala         | 57 +++++++++++++++++++++-
 src/main/scala/chisel3/util/Enum.scala             | 41 ++++++----------
 src/test/scala/chiselTests/Risc.scala              |  2 +-
 src/test/scala/chiselTests/VendingMachine.scala    |  2 +-
 5 files changed, 72 insertions(+), 47 deletions(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index cab1a82e..035ac213 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -54,8 +54,6 @@ sealed abstract class Bits(width: Width, override val litArg: Option[LitArg])
   // Arguments for: self-checking code (can't do arithmetic on bits)
   // Arguments against: generates down to a FIRRTL UInt anyways
 
-  private[chisel3] def fromInt(x: BigInt, w: Int): this.type
-
   private[chisel3] def flatten: IndexedSeq[Bits] = IndexedSeq(this)
 
   def cloneType: this.type = cloneTypeWidth(width)
@@ -402,9 +400,6 @@ sealed class UInt private[core] (width: Width, lit: Option[ULit] = None)
     new UInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"UInt$width"
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asUInt(width.W).asInstanceOf[this.type]
-
   // TODO: refactor to share documentation with Num or add independent scaladoc
   final def unary_- (): UInt = macro SourceInfoTransform.noArg
   final def unary_-% (): UInt = macro SourceInfoTransform.noArg
@@ -562,9 +557,6 @@ sealed class SInt private[core] (width: Width, lit: Option[SLit] = None)
     new SInt(w).asInstanceOf[this.type]
   private[chisel3] def toType = s"SInt$width"
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type =
-    value.asSInt(width.W).asInstanceOf[this.type]
-
   final def unary_- (): SInt = macro SourceInfoTransform.noArg
   final def unary_-% (): SInt = macro SourceInfoTransform.noArg
 
@@ -696,11 +688,6 @@ sealed class Bool(lit: Option[ULit] = None) extends UInt(1.W, lit) {
     new Bool().asInstanceOf[this.type]
   }
 
-  override private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
-    require((value == 0 || value == 1) && width == 1)
-    (value == 1).asBool.asInstanceOf[this.type]
-  }
-
   // REVIEW TODO: Why does this need to exist and have different conventions
   // than Bits?
   final def & (that: Bool): Bool = macro SourceInfoTransform.thatArg
@@ -823,10 +810,6 @@ sealed class FixedPoint private (width: Width, val binaryPoint: BinaryPoint, lit
     case _ => this badConnect that
   }
 
-  private[chisel3] def fromInt(value: BigInt, width: Int): this.type = {
-    throwException(s"Don't use $this.fromInt($value, $width): Use literal constructors instead")
-  }
-
   final def unary_- (): FixedPoint = macro SourceInfoTransform.noArg
   final def unary_-% (): FixedPoint = macro SourceInfoTransform.noArg
 
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 51176d9d..4ffd0b86 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -250,7 +250,62 @@ package object Chisel {     // scalastyle:ignore package.object.name
   type Queue[T <: Data] = chisel3.util.Queue[T]
   val Queue = chisel3.util.Queue
 
-  val Enum = chisel3.util.Enum
+  object Enum extends chisel3.util.Enum {
+    /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
+      *
+      * nodeType must be of UInt type (note that Bits() creates a UInt) with unspecified width.
+      *
+      * @example {{{
+      * val state_on :: state_off :: Nil = Enum(UInt(), 2)
+      * val current_state = UInt()
+      * switch (current_state) {
+      *   is (state_on) {
+      *      ...
+      *   }
+      *   if (state_off) {
+      *      ...
+      *   }
+      * }
+      * }}}
+      */
+    def apply[T <: Bits](nodeType: T, n: Int): List[T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      apply(n).asInstanceOf[List[T]]
+    }
+
+    /** An old Enum API that returns a map of symbols to UInts.
+      *
+      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
+      * understands and can check, map accesses can't be compile-time checked and typos may not be
+      * caught until runtime.
+      *
+      * Despite being deprecated, this is not to be removed from the compatibility layer API.
+      * Deprecation is only to nag users to do something safer.
+      */
+    @deprecated("Use list-based Enum", "not soon enough")
+    def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+    }
+
+    /** An old Enum API that returns a map of symbols to UInts.
+      *
+      * Unlike the new list-based Enum, which can be unpacked into vals that the compiler
+      * understands and can check, map accesses can't be compile-time checked and typos may not be
+      * caught until runtime.
+      *
+      * Despite being deprecated, this is not to be removed from the compatibility layer API.
+      * Deprecation is only to nag users to do something safer.
+      */
+    @deprecated("Use list-based Enum", "not soon enough")
+    def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = {
+      require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+      require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+      (l zip createValues(l.length)).toMap.asInstanceOf[Map[Symbol, T]]
+    }
+  }
 
   val LFSR16 = chisel3.util.LFSR16
 
diff --git a/src/main/scala/chisel3/util/Enum.scala b/src/main/scala/chisel3/util/Enum.scala
index 55b595ee..45aee62a 100644
--- a/src/main/scala/chisel3/util/Enum.scala
+++ b/src/main/scala/chisel3/util/Enum.scala
@@ -7,15 +7,15 @@ package chisel3.util
 
 import chisel3._
 
-object Enum {
+trait Enum {
   /** Returns a sequence of Bits subtypes with values from 0 until n. Helper method. */
-  private def createValues[T <: Bits](nodeType: T, n: Int): Seq[T] =
-    (0 until n).map(x => nodeType.fromInt(x, log2Up(n)))
+  protected def createValues(n: Int): Seq[UInt] =
+    (0 until n).map(_.U(log2Up(n).W))
 
-  /** Returns n unique values of the specified type. Can be used with unpacking to define enums.
+  /** Returns n unique UInt values, use with unpacking to specify an enumeration.
     *
     * @example {{{
-    * val state_on :: state_off :: Nil = Enum(UInt(), 2)
+    * val state_on :: state_off :: Nil = Enum(2)
     * val current_state = UInt()
     * switch (current_state) {
     *   is (state_on) {
@@ -26,28 +26,15 @@ object Enum {
     *   }
     * }
     * }}}
-    *
     */
-  def apply[T <: Bits](nodeType: T, n: Int): List[T] = createValues(nodeType, n).toList
-
-  /** Returns a map of the input symbols to unique values of the specified type.
-    *
-    * @example {{{
-    * val states = Enum(UInt(), 'on, 'off)
-    * val current_state = UInt()
-    * switch (current_state) {
-    *   is (states('on)) {
-    *     ...
-    *   }
-    *   if (states('off)) {
-    *     ..
-    *   }
-    * }
-    * }}}
-    */
-  def apply[T <: Bits](nodeType: T, l: Symbol *): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+  def apply(n: Int): List[UInt] = createValues(n).toList
+}
 
-  /** Returns a map of the input symbols to unique values of the specified type.
-    */
-  def apply[T <: Bits](nodeType: T, l: List[Symbol]): Map[Symbol, T] = (l zip createValues(nodeType, l.length)).toMap
+object Enum extends Enum {
+  @deprecated("use Enum(n)", "chisel3, will be removed soon")
+  def apply[T <: Bits](nodeType: T, n: Int): List[T] = {
+    require(nodeType.isInstanceOf[UInt], "Only UInt supported for enums")
+    require(!nodeType.widthKnown, "Bit width may no longer be specified for enums")
+    apply(n).asInstanceOf[List[T]]
+  }
 }
diff --git a/src/test/scala/chiselTests/Risc.scala b/src/test/scala/chiselTests/Risc.scala
index 57586c97..0d03ff65 100644
--- a/src/test/scala/chiselTests/Risc.scala
+++ b/src/test/scala/chiselTests/Risc.scala
@@ -19,7 +19,7 @@ class Risc extends Module {
   val code = Mem(memSize, Bits(32.W))
   val pc   = Reg(init=0.U(8.W))
 
-  val add_op :: imm_op :: Nil = Enum(Bits(8.W), 2)
+  val add_op :: imm_op :: Nil = Enum(2)
 
   val inst = code(pc)
   val op   = inst(31,24)
diff --git a/src/test/scala/chiselTests/VendingMachine.scala b/src/test/scala/chiselTests/VendingMachine.scala
index c474430b..712b5b7a 100644
--- a/src/test/scala/chiselTests/VendingMachine.scala
+++ b/src/test/scala/chiselTests/VendingMachine.scala
@@ -12,7 +12,7 @@ class VendingMachine extends Module {
     val valid  = Output(Bool())
   })
   val c = 5.U(3.W)
-  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(UInt(), 5)
+  val sIdle :: s5 :: s10 :: s15 :: sOk :: Nil = Enum(5)
   val state = Reg(init = sIdle)
   when (state === sIdle) {
     when (io.nickel) { state := s5 }
-- 
cgit v1.2.3


From 7680363982b02f53e9f76f5d5e242e44f17da6f7 Mon Sep 17 00:00:00 2001
From: Richard Lin
Date: Tue, 29 Nov 2016 16:37:13 -0800
Subject: Add feature warnings to build, fix feature warnings, fix some
 documentation (#387)

---
 build.sbt                                                  | 2 +-
 chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala | 2 +-
 src/main/scala/chisel3/compatibility.scala                 | 2 +-
 src/main/scala/chisel3/package.scala                       | 8 +++++---
 src/main/scala/chisel3/testers/TesterDriver.scala          | 2 +-
 src/main/scala/chisel3/util/ImplicitConversions.scala      | 2 ++
 src/main/scala/chisel3/util/Valid.scala                    | 6 ++++--
 7 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/build.sbt b/build.sbt
index ba629250..2ce1f523 100644
--- a/build.sbt
+++ b/build.sbt
@@ -19,7 +19,7 @@ lazy val commonSettings = Seq (
   git.remoteRepo := "git@github.com:ucb-bar/chisel3.git",
   autoAPIMappings := true,
   scalaVersion := "2.11.7",
-  scalacOptions := Seq("-deprecation")
+  scalacOptions := Seq("-deprecation", "-feature")
 )
 
 val defaultVersions = Map("firrtl" -> "1.1-SNAPSHOT")
diff --git a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
index 17354799..9bbf9d0e 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Aggregate.scala
@@ -225,7 +225,7 @@ sealed class Vec[T <: Data] private (gen: => T, val length: Int)
   private[chisel3] lazy val flatten: IndexedSeq[Bits] =
     (0 until length).flatMap(i => this.apply(i).flatten)
 
-  for ((elt, i) <- self zipWithIndex)
+  for ((elt, i) <- self.zipWithIndex)
     elt.setRef(this, i)
 
   /** Default "pretty-print" implementation
diff --git a/src/main/scala/chisel3/compatibility.scala b/src/main/scala/chisel3/compatibility.scala
index 4ffd0b86..613385af 100644
--- a/src/main/scala/chisel3/compatibility.scala
+++ b/src/main/scala/chisel3/compatibility.scala
@@ -120,7 +120,7 @@ package object Chisel {     // scalastyle:ignore package.object.name
     */
   trait BoolFactory extends chisel3.core.BoolFactory {
     /** Creates Bool literal.
-     */
+      */
     def apply(x: Boolean): Bool = x.B
 
     /** Create a UInt with a specified direction and width - compatibility with Chisel2. */
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 449f4ea5..e4e64b89 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -1,6 +1,8 @@
 // See LICENSE for license details.
 
 package object chisel3 {    // scalastyle:ignore package.object.name
+  import scala.language.implicitConversions
+
   import internal.firrtl.Width
 
   import util.BitPat
@@ -267,11 +269,11 @@ package object chisel3 {    // scalastyle:ignore package.object.name
       import internal.firrtl.NumericBound
 
       /** Specifies a range using mathematical range notation. Variables can be interpolated using
-       *  standard string interpolation syntax.
+        * standard string interpolation syntax.
         * @example {{{
         * UInt(range"[0, 2)")
-        * UInt(range"[0, $myInt)")
-        * UInt(range"[0, ${myInt + 2})")
+        * UInt(range"[0, \$myInt)")
+        * UInt(range"[0, \${myInt + 2})")
         * }}}
         */
       def range(args: Any*): (NumericBound[Int], NumericBound[Int]) = macro chisel3.internal.RangeTransform.apply
diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala
index 76b9a2e9..83f3c796 100644
--- a/src/main/scala/chisel3/testers/TesterDriver.scala
+++ b/src/main/scala/chisel3/testers/TesterDriver.scala
@@ -14,7 +14,7 @@ object TesterDriver extends BackendCompilationUtilities {
       throw new FileNotFoundException(s"Resource '$name'")
     }
     val out = new FileOutputStream(file)
-    Iterator.continually(in.read).takeWhile(-1 !=).foreach(out.write)
+    Iterator.continually(in.read).takeWhile(-1 != _).foreach(out.write)
     out.close()
   }
 
diff --git a/src/main/scala/chisel3/util/ImplicitConversions.scala b/src/main/scala/chisel3/util/ImplicitConversions.scala
index c2ba710d..712975a7 100644
--- a/src/main/scala/chisel3/util/ImplicitConversions.scala
+++ b/src/main/scala/chisel3/util/ImplicitConversions.scala
@@ -4,6 +4,8 @@ package chisel3.util
 
 import chisel3._
 
+import scala.language.implicitConversions
+
 object ImplicitConversions {
   // The explicit fromIntToLiteral resolves an ambiguous conversion between fromIntToLiteral and
   // UInt.asUInt.
diff --git a/src/main/scala/chisel3/util/Valid.scala b/src/main/scala/chisel3/util/Valid.scala
index 49a6f515..0229b7f8 100644
--- a/src/main/scala/chisel3/util/Valid.scala
+++ b/src/main/scala/chisel3/util/Valid.scala
@@ -52,10 +52,12 @@ object Pipe
 
 class Pipe[T <: Data](gen: T, latency: Int = 1) extends Module
 {
-  val io = IO(new Bundle {
+  class PipeIO extends Bundle {
     val enq = Input(Valid(gen))
     val deq = Output(Valid(gen))
-  })
+  }
+
+  val io = IO(new PipeIO)
 
   io.deq <> Pipe(io.enq, latency)
 }
-- 
cgit v1.2.3


From 6725dbd501e3d3a0d6a626f69473115069ac3b34 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 1 Dec 2016 17:34:39 -0800
Subject: Fix spelling of "specified". (#392)

---
 chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
index 262b939f..699cc13c 100644
--- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala
@@ -64,7 +64,7 @@ abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
   protected def minWidth: Int
   if (forcedWidth) {
     require(widthArg.get >= minWidth,
-      s"The literal value ${num} was elaborated with a specificed width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
+      s"The literal value ${num} was elaborated with a specified width of ${widthArg.get} bits, but at least ${minWidth} bits are required.")
   }
 }
 
-- 
cgit v1.2.3


From 76818e50c06f26c44788168cf09754135ad6a841 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 2 Dec 2016 08:40:29 -0800
Subject: Update installation instructions to include firrtl publish-local.

---
 README.md | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/README.md b/README.md
index d2093e57..ea9cf496 100644
--- a/README.md
+++ b/README.md
@@ -72,6 +72,10 @@ This will walk you through installing Chisel and its dependencies:
         ```
         sudo update-alternatives --config java
         ```
+  1. Locally publish this version of firrtl so it is available to satisfy the chisel3 library dependency:
+        ```
+        sbt publish-local
+        ```
   1. Add the FIRRTL executable to your PATH. One way is to add this line to your
     `.bashrc`:
 
-- 
cgit v1.2.3


From 44a814b1d77a7e055cb7ac863b3dd6ae92c6cf08 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Fri, 2 Dec 2016 10:13:23 -0800
Subject: Insert missing newline for sbt-publish.

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index ea9cf496..00b7ab94 100644
--- a/README.md
+++ b/README.md
@@ -73,6 +73,7 @@ This will walk you through installing Chisel and its dependencies:
         sudo update-alternatives --config java
         ```
   1. Locally publish this version of firrtl so it is available to satisfy the chisel3 library dependency:
+
         ```
         sbt publish-local
         ```
-- 
cgit v1.2.3