From d20591e0d030d5c380e279999659fbfa9f41d3d3 Mon Sep 17 00:00:00 2001
From: ducky
Date: Thu, 19 Nov 2015 16:03:53 -0800
Subject: Split internal and FIRRTL packages

---
 src/main/scala/Chisel/Aggregate.scala        |   6 +-
 src/main/scala/Chisel/BitPat.scala           |   2 +-
 src/main/scala/Chisel/Bits.scala             |   7 +-
 src/main/scala/Chisel/Data.scala             |   5 +-
 src/main/scala/Chisel/Driver.scala           |   3 +
 src/main/scala/Chisel/Mem.scala              |   5 +-
 src/main/scala/Chisel/Module.scala           |   8 +-
 src/main/scala/Chisel/Reg.scala              |   5 +-
 src/main/scala/Chisel/When.scala             |   5 +-
 src/main/scala/Chisel/firrtl/Emitter.scala   |  74 +++++++++++++
 src/main/scala/Chisel/firrtl/IR.scala        | 159 +++++++++++++++++++++++++++
 src/main/scala/Chisel/internal/Builder.scala |  14 ++-
 src/main/scala/Chisel/internal/Error.scala   |   9 +-
 src/main/scala/Chisel/ir/Emitter.scala       |  73 ------------
 src/main/scala/Chisel/ir/IR.scala            | 157 --------------------------
 src/main/scala/Chisel/util/Conditional.scala |   6 +-
 src/test/scala/chiselTests/ChiselSpec.scala  |   2 +-
 src/test/scala/chiselTests/Reg.scala         |   2 +-
 18 files changed, 289 insertions(+), 253 deletions(-)
 create mode 100644 src/main/scala/Chisel/firrtl/Emitter.scala
 create mode 100644 src/main/scala/Chisel/firrtl/IR.scala
 delete mode 100644 src/main/scala/Chisel/ir/Emitter.scala
 delete mode 100644 src/main/scala/Chisel/ir/IR.scala

diff --git a/src/main/scala/Chisel/Aggregate.scala b/src/main/scala/Chisel/Aggregate.scala
index 8a0f20af..1506833c 100644
--- a/src/main/scala/Chisel/Aggregate.scala
+++ b/src/main/scala/Chisel/Aggregate.scala
@@ -1,9 +1,13 @@
 // See LICENSE for license details.
 
 package Chisel
+
 import scala.collection.immutable.ListMap
 import scala.collection.mutable.{ArrayBuffer, HashSet, LinkedHashMap}
-import Builder.pushCommand
+
+import internal._
+import internal.Builder.pushCommand
+import firrtl._
 
 /** An abstract class for data types that solely consist of (are an aggregate
   * of) other Data objects.
diff --git a/src/main/scala/Chisel/BitPat.scala b/src/main/scala/Chisel/BitPat.scala
index d7b01ba6..b4138992 100644
--- a/src/main/scala/Chisel/BitPat.scala
+++ b/src/main/scala/Chisel/BitPat.scala
@@ -21,7 +21,7 @@ object BitPat {
     var mask = BigInt(0)
     for (d <- x.tail) {
       if (d != '_') {
-        if (!"01?".contains(d)) Builder.error({"Literal: " + x + " contains illegal character: " + d})
+        require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d)
         mask = (mask << 1) + (if (d == '?') 0 else 1)
         bits = (bits << 1) + (if (d == '1') 1 else 0)
       }
diff --git a/src/main/scala/Chisel/Bits.scala b/src/main/scala/Chisel/Bits.scala
index 41f13c48..b6ee6d1a 100644
--- a/src/main/scala/Chisel/Bits.scala
+++ b/src/main/scala/Chisel/Bits.scala
@@ -1,8 +1,11 @@
 // See LICENSE for license details.
 
 package Chisel
-import Builder.pushOp
-import PrimOp._
+
+import internal._
+import internal.Builder.pushOp
+import firrtl._
+import firrtl.PrimOp._
 
 /** Element is a leaf data type: it cannot contain other Data objects. Example
   * uses are for representing primitive data types, like integers and bits.
diff --git a/src/main/scala/Chisel/Data.scala b/src/main/scala/Chisel/Data.scala
index 679b8eb8..f9b277e1 100644
--- a/src/main/scala/Chisel/Data.scala
+++ b/src/main/scala/Chisel/Data.scala
@@ -1,7 +1,10 @@
 // See LICENSE for license details.
 
 package Chisel
-import Builder.pushCommand
+
+import internal._
+import internal.Builder.pushCommand
+import firrtl._
 
 sealed abstract class Direction(name: String) {
   override def toString: String = name
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index dd78ab8d..a31786d9 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -5,6 +5,9 @@ package Chisel
 import scala.sys.process._
 import java.io._
 
+import internal._
+import firrtl._
+
 trait FileSystemUtilities {
   def writeTempFile(pre: String, post: String, contents: String): File = {
     val t = File.createTempFile(pre, post)
diff --git a/src/main/scala/Chisel/Mem.scala b/src/main/scala/Chisel/Mem.scala
index f4003c25..bd27a9c7 100644
--- a/src/main/scala/Chisel/Mem.scala
+++ b/src/main/scala/Chisel/Mem.scala
@@ -1,7 +1,10 @@
 // See LICENSE for license details.
 
 package Chisel
-import Builder.pushCommand
+
+import internal._
+import internal.Builder.pushCommand
+import firrtl._
 
 object Mem {
   @deprecated("Mem argument order should be size, t; this will be removed by the official release", "chisel3")
diff --git a/src/main/scala/Chisel/Module.scala b/src/main/scala/Chisel/Module.scala
index f799a7ce..4284bbc4 100644
--- a/src/main/scala/Chisel/Module.scala
+++ b/src/main/scala/Chisel/Module.scala
@@ -1,9 +1,13 @@
 // See LICENSE for license details.
 
 package Chisel
+
 import scala.collection.mutable.{ArrayBuffer, HashSet}
-import Builder.pushCommand
-import Builder.dynamicContext
+
+import internal._
+import internal.Builder.pushCommand
+import internal.Builder.dynamicContext
+import firrtl._
 
 object Module {
   /** A wrapper method that all Module instantiations must be wrapped in
diff --git a/src/main/scala/Chisel/Reg.scala b/src/main/scala/Chisel/Reg.scala
index 098f3922..21415362 100644
--- a/src/main/scala/Chisel/Reg.scala
+++ b/src/main/scala/Chisel/Reg.scala
@@ -1,7 +1,10 @@
 // See LICENSE for license details.
 
 package Chisel
-import Builder.pushCommand
+
+import internal._
+import internal.Builder.pushCommand
+import firrtl._
 
 object Reg {
   private[Chisel] def makeType[T <: Data](t: T = null, next: T = null, init: T = null): T = {
diff --git a/src/main/scala/Chisel/When.scala b/src/main/scala/Chisel/When.scala
index a051e52c..7b8d60c2 100644
--- a/src/main/scala/Chisel/When.scala
+++ b/src/main/scala/Chisel/When.scala
@@ -1,7 +1,10 @@
 // See LICENSE for license details.
 
 package Chisel
-import Builder.pushCommand
+
+import internal._
+import internal.Builder.pushCommand
+import firrtl._
 
 object when {  // scalastyle:ignore object.name
   /** Create a `when` condition block, where whether a block of logic is
diff --git a/src/main/scala/Chisel/firrtl/Emitter.scala b/src/main/scala/Chisel/firrtl/Emitter.scala
new file mode 100644
index 00000000..bcc566c5
--- /dev/null
+++ b/src/main/scala/Chisel/firrtl/Emitter.scala
@@ -0,0 +1,74 @@
+// See LICENSE for license details.
+
+package Chisel.firrtl
+import Chisel._
+
+private class Emitter(circuit: Circuit) {
+  override def toString: String = res.toString
+
+  private def emitPort(e: Port): String =
+    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
+  private def emit(e: Command, ctx: Component): String = e match {
+    case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})"
+    case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
+    case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
+    case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
+    case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
+    case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
+    case e: DefAccessor[_] => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
+    case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
+    case e: BulkConnect => s"${e.loc1.fullName(ctx)} <> ${e.loc2.fullName(ctx)}"
+    case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
+    case e: DefInstance => {
+      val modName = moduleMap.getOrElse(e.id.name, e.id.name)
+      s"inst ${e.name} of $modName"
+    }
+
+    case w: WhenBegin =>
+      indent()
+      s"when ${w.pred.fullName(ctx)} :"
+    case _: WhenElse =>
+      indent()
+      "else :"
+    case _: WhenEnd =>
+      unindent()
+      "skip"
+  }
+  private def emitBody(m: Component) = {
+    val me = new StringBuilder
+    withIndent {
+      for (p <- m.ports)
+        me ++= newline + emitPort(p)
+      me ++= newline
+      for (cmd <- m.commands)
+        me ++= newline + emit(cmd, m)
+      me ++= newline
+    }
+    me
+  }
+
+  private val bodyMap = collection.mutable.HashMap[StringBuilder, String]()
+  private val moduleMap = collection.mutable.HashMap[String, String]()
+
+  private def emit(m: Component): String = {
+    val body = emitBody(m)
+    bodyMap get body match {
+      case Some(name) =>
+        moduleMap(m.name) = name
+        ""
+      case None =>
+        bodyMap(body) = m.name
+        newline + s"module ${m.name} : " + body
+    }
+  }
+
+  private var indentLevel = 0
+  private def newline = "\n" + ("  " * indentLevel)
+  private def indent(): Unit = indentLevel += 1
+  private def unindent() { require(indentLevel > 0); indentLevel -= 1 }
+  private def withIndent(f: => Unit) { indent(); f; unindent() }
+
+  private val res = new StringBuilder(s"circuit ${circuit.name} : ")
+  withIndent { circuit.components.foreach(c => res ++= emit(c)) }
+  res ++= newline
+}
diff --git a/src/main/scala/Chisel/firrtl/IR.scala b/src/main/scala/Chisel/firrtl/IR.scala
new file mode 100644
index 00000000..458e6ac5
--- /dev/null
+++ b/src/main/scala/Chisel/firrtl/IR.scala
@@ -0,0 +1,159 @@
+// See LICENSE for license details.
+
+package Chisel.firrtl
+import Chisel._
+import Chisel.internal._
+
+case class PrimOp(val name: String) {
+  override def toString: String = name
+}
+
+object PrimOp {
+  val AddOp = PrimOp("add")
+  val AddModOp = PrimOp("addw")
+  val SubOp = PrimOp("sub")
+  val SubModOp = PrimOp("subw")
+  val TimesOp = PrimOp("mul")
+  val DivideOp = PrimOp("div")
+  val ModOp = PrimOp("mod")
+  val ShiftLeftOp = PrimOp("shl")
+  val ShiftRightOp = PrimOp("shr")
+  val DynamicShiftLeftOp = PrimOp("dshl")
+  val DynamicShiftRightOp = PrimOp("dshr")
+  val BitAndOp = PrimOp("and")
+  val BitOrOp = PrimOp("or")
+  val BitXorOp = PrimOp("xor")
+  val BitNotOp = PrimOp("not")
+  val ConcatOp = PrimOp("cat")
+  val BitSelectOp = PrimOp("bit")
+  val BitsExtractOp = PrimOp("bits")
+  val LessOp = PrimOp("lt")
+  val LessEqOp = PrimOp("leq")
+  val GreaterOp = PrimOp("gt")
+  val GreaterEqOp = PrimOp("geq")
+  val EqualOp = PrimOp("eq")
+  val PadOp = PrimOp("pad")
+  val NotEqualOp = PrimOp("neq")
+  val NegOp = PrimOp("neg")
+  val MultiplexOp = PrimOp("mux")
+  val XorReduceOp = PrimOp("xorr")
+  val ConvertOp = PrimOp("cvt")
+  val AsUIntOp = PrimOp("asUInt")
+  val AsSIntOp = PrimOp("asSInt")
+}
+
+abstract class Arg {
+  def fullName(ctx: Component): String = name
+  def name: String
+}
+
+case class Node(id: HasId) extends Arg {
+  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
+  def name: String = id.getRef.name
+}
+
+abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
+  private[Chisel] def forcedWidth = widthArg.known
+  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
+
+  protected def minWidth: Int
+  if (forcedWidth) {
+    require(widthArg.get >= minWidth)
+  }
+}
+
+case class ILit(n: BigInt) extends Arg {
+  def name: String = n.toString
+}
+
+case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
+  def name: String = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
+  def minWidth: Int = 1 max n.bitLength
+
+  require(n >= 0, s"UInt literal ${n} is negative")
+}
+
+case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
+  def name: String = {
+    val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
+    s"asSInt(${ULit(unsigned, width).name})"
+  }
+  def minWidth: Int = 1 + n.bitLength
+}
+
+case class Ref(name: String) extends Arg
+case class ModuleIO(mod: Module, name: String) extends Arg {
+  override def fullName(ctx: Component): String =
+    if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
+}
+case class Slot(imm: Node, name: String) extends Arg {
+  override def fullName(ctx: Component): String =
+    if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}"
+}
+case class Index(imm: Arg, value: Int) extends Arg {
+  def name: String = s"[$value]"
+  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[$value]"
+}
+
+object Width {
+  def apply(x: Int): Width = KnownWidth(x)
+  def apply(): Width = UnknownWidth()
+}
+
+sealed abstract class Width {
+  type W = Int
+  def max(that: Width): Width = this.op(that, _ max _)
+  def + (that: Width): Width = this.op(that, _ + _)
+  def + (that: Int): Width = this.op(this, (a, b) => a + that)
+  def shiftRight(that: Int): Width = this.op(this, (a, b) => 0 max (a - that))
+  def dynamicShiftLeft(that: Width): Width =
+    this.op(that, (a, b) => a + (1 << b) - 1)
+
+  def known: Boolean
+  def get: W
+  protected def op(that: Width, f: (W, W) => W): Width
+}
+
+sealed case class UnknownWidth() extends Width {
+  def known: Boolean = false
+  def get: Int = None.get
+  def op(that: Width, f: (W, W) => W): Width = this
+  override def toString: String = "?"
+}
+
+sealed case class KnownWidth(value: Int) extends Width {
+  require(value >= 0)
+  def known: Boolean = true
+  def get: Int = value
+  def op(that: Width, f: (W, W) => W): Width = that match {
+    case KnownWidth(x) => KnownWidth(f(value, x))
+    case _ => that
+  }
+  override def toString: String = value.toString
+}
+
+abstract class Command
+abstract class Definition extends Command {
+  def id: HasId
+  def name: String = id.getRef.name
+}
+case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
+case class DefWire(id: Data) extends Definition
+case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
+case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
+case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
+case class DefAccessor[T <: Data](id: T, source: Node, direction: Direction, index: Arg) extends Definition
+case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
+case class DefPoison[T <: Data](id: T) extends Definition
+case class WhenBegin(pred: Arg) extends Command
+case class WhenElse() extends Command
+case class WhenEnd() extends Command
+case class Connect(loc: Node, exp: Arg) extends Command
+case class BulkConnect(loc1: Node, loc2: Node) extends Command
+case class ConnectInit(loc: Node, exp: Arg) extends Command
+case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
+case class Port(id: Data, dir: Direction)
+
+case class Circuit(name: String, components: Seq[Component], refMap: RefMap) {
+  def emit: String = new Emitter(this).toString
+}
diff --git a/src/main/scala/Chisel/internal/Builder.scala b/src/main/scala/Chisel/internal/Builder.scala
index 79d5d6aa..385e25a2 100644
--- a/src/main/scala/Chisel/internal/Builder.scala
+++ b/src/main/scala/Chisel/internal/Builder.scala
@@ -1,10 +1,14 @@
 // See LICENSE for license details.
 
-package Chisel
+package Chisel.internal
+
 import scala.util.DynamicVariable
 import scala.collection.mutable.{ArrayBuffer, HashMap}
 
-private class Namespace(parent: Option[Namespace], keywords: Set[String]) {
+import Chisel._
+import Chisel.firrtl._
+
+private[Chisel] class Namespace(parent: Option[Namespace], keywords: Set[String]) {
   private var i = 0L
   private val names = collection.mutable.HashSet[String]()
 
@@ -28,7 +32,7 @@ private class Namespace(parent: Option[Namespace], keywords: Set[String]) {
   def child: Namespace = child(Set())
 }
 
-private class IdGen {
+private[Chisel] class IdGen {
   private var counter = -1L
   def next: Long = {
     counter += 1
@@ -68,7 +72,7 @@ class RefMap {
   def apply(id: HasId): Arg = _refmap(id._id)
 }
 
-private class DynamicContext {
+private[Chisel] class DynamicContext {
   val idGen = new IdGen
   val globalNamespace = new Namespace(None, Set())
   val globalRefMap = new RefMap
@@ -77,7 +81,7 @@ private class DynamicContext {
   val errors = new ErrorLog
 }
 
-private object Builder {
+private[Chisel] object Builder {
   // All global mutable state must be referenced via dynamicContextVar!!
   private val dynamicContextVar = new DynamicVariable[Option[DynamicContext]](None)
 
diff --git a/src/main/scala/Chisel/internal/Error.scala b/src/main/scala/Chisel/internal/Error.scala
index 4bfcb555..6c4c0880 100644
--- a/src/main/scala/Chisel/internal/Error.scala
+++ b/src/main/scala/Chisel/internal/Error.scala
@@ -1,17 +1,20 @@
 // See LICENSE for license details.
 
-package Chisel
+package Chisel.internal
+
 import scala.collection.mutable.ArrayBuffer
 
+import Chisel._
+
 class ChiselException(message: String, cause: Throwable) extends Exception(message, cause)
 
-private object throwException {
+private[Chisel] object throwException {
   def apply(s: String, t: Throwable = null): Nothing =
     throw new ChiselException(s, t)
 }
 
 /** Records and reports runtime errors and warnings. */
-private class ErrorLog {
+private[Chisel] class ErrorLog {
   def hasErrors: Boolean = errors.exists(_.isFatal)
 
   /** Log an error message */
diff --git a/src/main/scala/Chisel/ir/Emitter.scala b/src/main/scala/Chisel/ir/Emitter.scala
deleted file mode 100644
index b4689d61..00000000
--- a/src/main/scala/Chisel/ir/Emitter.scala
+++ /dev/null
@@ -1,73 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-private class Emitter(circuit: Circuit) {
-  override def toString: String = res.toString
-
-  private def emitPort(e: Port): String =
-    s"${e.dir} ${e.id.getRef.name} : ${e.id.toType}"
-  private def emit(e: Command, ctx: Component): String = e match {
-    case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})"
-    case e: DefWire => s"wire ${e.name} : ${e.id.toType}"
-    case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}"
-    case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}"
-    case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
-    case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}], ${e.clock.fullName(ctx)}"
-    case e: DefAccessor[_] => s"infer accessor ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}]"
-    case e: Connect => s"${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
-    case e: BulkConnect => s"${e.loc1.fullName(ctx)} <> ${e.loc2.fullName(ctx)}"
-    case e: ConnectInit => s"onreset ${e.loc.fullName(ctx)} := ${e.exp.fullName(ctx)}"
-    case e: DefInstance => {
-      val modName = moduleMap.getOrElse(e.id.name, e.id.name)
-      s"inst ${e.name} of $modName"
-    }
-
-    case w: WhenBegin =>
-      indent()
-      s"when ${w.pred.fullName(ctx)} :"
-    case _: WhenElse =>
-      indent()
-      "else :"
-    case _: WhenEnd =>
-      unindent()
-      "skip"
-  }
-  private def emitBody(m: Component) = {
-    val me = new StringBuilder
-    withIndent {
-      for (p <- m.ports)
-        me ++= newline + emitPort(p)
-      me ++= newline
-      for (cmd <- m.commands)
-        me ++= newline + emit(cmd, m)
-      me ++= newline
-    }
-    me
-  }
-
-  private val bodyMap = collection.mutable.HashMap[StringBuilder, String]()
-  private val moduleMap = collection.mutable.HashMap[String, String]()
-
-  private def emit(m: Component): String = {
-    val body = emitBody(m)
-    bodyMap get body match {
-      case Some(name) =>
-        moduleMap(m.name) = name
-        ""
-      case None =>
-        bodyMap(body) = m.name
-        newline + s"module ${m.name} : " + body
-    }
-  }
-
-  private var indentLevel = 0
-  private def newline = "\n" + ("  " * indentLevel)
-  private def indent(): Unit = indentLevel += 1
-  private def unindent() { require(indentLevel > 0); indentLevel -= 1 }
-  private def withIndent(f: => Unit) { indent(); f; unindent() }
-
-  private val res = new StringBuilder(s"circuit ${circuit.name} : ")
-  withIndent { circuit.components.foreach(c => res ++= emit(c)) }
-  res ++= newline
-}
diff --git a/src/main/scala/Chisel/ir/IR.scala b/src/main/scala/Chisel/ir/IR.scala
deleted file mode 100644
index 106ad20c..00000000
--- a/src/main/scala/Chisel/ir/IR.scala
+++ /dev/null
@@ -1,157 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-case class PrimOp(val name: String) {
-  override def toString: String = name
-}
-
-object PrimOp {
-  val AddOp = PrimOp("add")
-  val AddModOp = PrimOp("addw")
-  val SubOp = PrimOp("sub")
-  val SubModOp = PrimOp("subw")
-  val TimesOp = PrimOp("mul")
-  val DivideOp = PrimOp("div")
-  val ModOp = PrimOp("mod")
-  val ShiftLeftOp = PrimOp("shl")
-  val ShiftRightOp = PrimOp("shr")
-  val DynamicShiftLeftOp = PrimOp("dshl")
-  val DynamicShiftRightOp = PrimOp("dshr")
-  val BitAndOp = PrimOp("and")
-  val BitOrOp = PrimOp("or")
-  val BitXorOp = PrimOp("xor")
-  val BitNotOp = PrimOp("not")
-  val ConcatOp = PrimOp("cat")
-  val BitSelectOp = PrimOp("bit")
-  val BitsExtractOp = PrimOp("bits")
-  val LessOp = PrimOp("lt")
-  val LessEqOp = PrimOp("leq")
-  val GreaterOp = PrimOp("gt")
-  val GreaterEqOp = PrimOp("geq")
-  val EqualOp = PrimOp("eq")
-  val PadOp = PrimOp("pad")
-  val NotEqualOp = PrimOp("neq")
-  val NegOp = PrimOp("neg")
-  val MultiplexOp = PrimOp("mux")
-  val XorReduceOp = PrimOp("xorr")
-  val ConvertOp = PrimOp("cvt")
-  val AsUIntOp = PrimOp("asUInt")
-  val AsSIntOp = PrimOp("asSInt")
-}
-
-abstract class Arg {
-  def fullName(ctx: Component): String = name
-  def name: String
-}
-
-case class Node(id: HasId) extends Arg {
-  override def fullName(ctx: Component): String = id.getRef.fullName(ctx)
-  def name: String = id.getRef.name
-}
-
-abstract class LitArg(val num: BigInt, widthArg: Width) extends Arg {
-  private[Chisel] def forcedWidth = widthArg.known
-  private[Chisel] def width: Width = if (forcedWidth) widthArg else Width(minWidth)
-
-  protected def minWidth: Int
-  if (forcedWidth) {
-    require(widthArg.get >= minWidth)
-  }
-}
-
-case class ILit(n: BigInt) extends Arg {
-  def name: String = n.toString
-}
-
-case class ULit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name: String = "UInt<" + width + ">(\"h0" + num.toString(16) + "\")"
-  def minWidth: Int = 1 max n.bitLength
-
-  require(n >= 0, s"UInt literal ${n} is negative")
-}
-
-case class SLit(n: BigInt, w: Width) extends LitArg(n, w) {
-  def name: String = {
-    val unsigned = if (n < 0) (BigInt(1) << width.get) + n else n
-    s"asSInt(${ULit(unsigned, width).name})"
-  }
-  def minWidth: Int = 1 + n.bitLength
-}
-
-case class Ref(name: String) extends Arg
-case class ModuleIO(mod: Module, name: String) extends Arg {
-  override def fullName(ctx: Component): String =
-    if (mod eq ctx.id) name else s"${mod.getRef.name}.$name"
-}
-case class Slot(imm: Node, name: String) extends Arg {
-  override def fullName(ctx: Component): String =
-    if (imm.fullName(ctx).isEmpty) name else s"${imm.fullName(ctx)}.${name}"
-}
-case class Index(imm: Arg, value: Int) extends Arg {
-  def name: String = s"[$value]"
-  override def fullName(ctx: Component): String = s"${imm.fullName(ctx)}[$value]"
-}
-
-object Width {
-  def apply(x: Int): Width = KnownWidth(x)
-  def apply(): Width = UnknownWidth()
-}
-
-sealed abstract class Width {
-  type W = Int
-  def max(that: Width): Width = this.op(that, _ max _)
-  def + (that: Width): Width = this.op(that, _ + _)
-  def + (that: Int): Width = this.op(this, (a, b) => a + that)
-  def shiftRight(that: Int): Width = this.op(this, (a, b) => 0 max (a - that))
-  def dynamicShiftLeft(that: Width): Width =
-    this.op(that, (a, b) => a + (1 << b) - 1)
-
-  def known: Boolean
-  def get: W
-  protected def op(that: Width, f: (W, W) => W): Width
-}
-
-sealed case class UnknownWidth() extends Width {
-  def known: Boolean = false
-  def get: Int = None.get
-  def op(that: Width, f: (W, W) => W): Width = this
-  override def toString: String = "?"
-}
-
-sealed case class KnownWidth(value: Int) extends Width {
-  require(value >= 0)
-  def known: Boolean = true
-  def get: Int = value
-  def op(that: Width, f: (W, W) => W): Width = that match {
-    case KnownWidth(x) => KnownWidth(f(value, x))
-    case _ => that
-  }
-  override def toString: String = value.toString
-}
-
-abstract class Command
-abstract class Definition extends Command {
-  def id: HasId
-  def name: String = id.getRef.name
-}
-case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition
-case class DefWire(id: Data) extends Definition
-case class DefRegister(id: Data, clock: Arg, reset: Arg) extends Definition
-case class DefMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
-case class DefSeqMemory(id: HasId, t: Data, size: Int, clock: Arg) extends Definition
-case class DefAccessor[T <: Data](id: T, source: Node, direction: Direction, index: Arg) extends Definition
-case class DefInstance(id: Module, ports: Seq[Port]) extends Definition
-case class DefPoison[T <: Data](id: T) extends Definition
-case class WhenBegin(pred: Arg) extends Command
-case class WhenElse() extends Command
-case class WhenEnd() extends Command
-case class Connect(loc: Node, exp: Arg) extends Command
-case class BulkConnect(loc1: Node, loc2: Node) extends Command
-case class ConnectInit(loc: Node, exp: Arg) extends Command
-case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg
-case class Port(id: Data, dir: Direction)
-
-case class Circuit(name: String, components: Seq[Component], refMap: RefMap) {
-  def emit: String = new Emitter(this).toString
-}
diff --git a/src/main/scala/Chisel/util/Conditional.scala b/src/main/scala/Chisel/util/Conditional.scala
index b0ac4491..9cab25ef 100644
--- a/src/main/scala/Chisel/util/Conditional.scala
+++ b/src/main/scala/Chisel/util/Conditional.scala
@@ -31,15 +31,15 @@ class SwitchContext[T <: Bits](cond: T) {
 object is {   // scalastyle:ignore object.name
   // Begin deprecation of non-type-parameterized is statements.
   def apply(v: Iterable[Bits])(block: => Unit) {
-    Builder.error("The 'is' keyword may not be used outside of a switch.")
+    require(false, "The 'is' keyword may not be used outside of a switch.")
   }
 
   def apply(v: Bits)(block: => Unit) {
-    Builder.error("The 'is' keyword may not be used outside of a switch.")
+    require(false, "The 'is' keyword may not be used outside of a switch.")
   }
 
   def apply(v: Bits, vr: Bits*)(block: => Unit) {
-    Builder.error("The 'is' keyword may not be used outside of a switch.")
+    require(false, "The 'is' keyword may not be used outside of a switch.")
   }
 }
 
diff --git a/src/test/scala/chiselTests/ChiselSpec.scala b/src/test/scala/chiselTests/ChiselSpec.scala
index 8848d4f5..000880e2 100644
--- a/src/test/scala/chiselTests/ChiselSpec.scala
+++ b/src/test/scala/chiselTests/ChiselSpec.scala
@@ -11,7 +11,7 @@ import Chisel.testers._
 /** Common utility functions for Chisel unit tests. */
 trait ChiselRunners {
   def execute(t: => BasicTester): Boolean = TesterDriver.execute(() => t)
-  def elaborate(t: => Module): Circuit = Driver.elaborate(() => t)
+  def elaborate(t: => Module): Unit = Driver.elaborate(() => t)
 }
 
 /** Spec base class for BDD-style testers. */
diff --git a/src/test/scala/chiselTests/Reg.scala b/src/test/scala/chiselTests/Reg.scala
index 55c92b45..f2620d88 100644
--- a/src/test/scala/chiselTests/Reg.scala
+++ b/src/test/scala/chiselTests/Reg.scala
@@ -8,7 +8,7 @@ import Chisel.testers.BasicTester
 
 class RegSpec extends ChiselFlatSpec {
   "A Reg" should "throw an exception if not given any parameters" in {
-    a [ChiselException] should be thrownBy {
+    a [Exception] should be thrownBy {
       val reg = Reg()
     }
   }
-- 
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