From cc84773743a092c901dbbcdf04bed01d310f2705 Mon Sep 17 00:00:00 2001 From: Abongwa Bonalais Date: Thu, 21 Oct 2021 07:08:10 +0100 Subject: Create CONTRIBUTING.md (#2191) * Create CONTRIBUTING.md * Update README.md Added guide for new contributors * Update CONTRIBUTING.md Co-authored-by: Megan Wachs * Update CONTRIBUTING.md Co-authored-by: Megan Wachs * Update README.md Co-authored-by: Megan Wachs * Update CONTRIBUTING.md Co-authored-by: Megan Wachs * Update CONTRIBUTING.md Co-authored-by: Megan Wachs * Update CONTRIBUTING.md Co-authored-by: Megan Wachs * Update README.md updated link to CONTRIBUTING.md * Update README.md updated link to CONTRIBUTING.md * Update README.md * Update README.md Co-authored-by: Megan Wachs * Update README.md Reposition contributing guide * Update CONTRIBUTING.md removed verilog guide Co-authored-by: Megan Wachs * Update README.md Added verilog tutorial link to useful resources area. Co-authored-by: Megan Wachs --- CONTRIBUTING.md | 14 ++++++++++++++ README.md | 3 +++ 2 files changed, 17 insertions(+) create mode 100644 CONTRIBUTING.md diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md new file mode 100644 index 00000000..5f55ac52 --- /dev/null +++ b/CONTRIBUTING.md @@ -0,0 +1,14 @@ +## GUIDE TO CONTRIBUTING + +1. If you need help on making a pull request, follow this [guide](https://docs.github.com/en/github/collaborating-with-pull-requests/proposing-changes-to-your-work-with-pull-requests/about-pull-requests). + +2. To understand how to compile and test chisel3 from the source code, follow the instructions in [SETUP.md](https://github.com/chipsalliance/chisel3/blob/master/SETUP.md). + +3. In order to contribute to chisel3, you'll need to sign the CLA agreement. You will be asked to sign it upon your first pull request. + + + +4. To introduce yourself and get help, you can join the [gitter](https://gitter.im/freechipsproject/chisel3) forum. If you have any questions or concerns, you can get help there. + +5. You can peruse the [good-first-issues](https://github.com/chipsalliance/chisel3/issues?q=is%3Aissue+is%3Aopen+label%3A%22good+first+issue%22) for easy tasks to start with. Another easy thing to start with is doing your own pass of the [website](https://www.chisel-lang.org/chisel3/docs/introduction.html) looking for typos, pages missing their titles, etc. The sources for the website are [here](https://github.com/chipsalliance/chisel3/tree/master/docs). + diff --git a/README.md b/README.md index 67adf976..1a780302 100644 --- a/README.md +++ b/README.md @@ -120,6 +120,8 @@ If you insist on setting up your own project, the magic SBT lines are: libraryDependencies += "edu.berkeley.cs" %% "chisel3" % "3.4.4" libraryDependencies += "edu.berkeley.cs" %% "chiseltest" % "0.3.4" % "test" ``` +### Guide For New Contributors +If you are trying to make a contribution to this project, please read [CONTRIBUTING.md](https://github.com/Burnleydev1/chisel3/blob/recent_PR/CONTRIBUTING.md) ### Design Verification @@ -136,6 +138,7 @@ These simulation-based verification tools are available for Chisel: - [**ScalaDoc**](https://www.chisel-lang.org/api/latest/chisel3/index.html), a listing, description, and examples of the functionality exposed by Chisel - [**Gitter**](https://gitter.im/freechipsproject/chisel3), where you can ask questions or discuss anything Chisel - [**Website**](https://www.chisel-lang.org) ([source](https://github.com/freechipsproject/www.chisel-lang.org/)) +- [**asic-world**](http://www.asic-world.com/verilog/veritut.html) If you aren't familiar with verilog, this is a good tutorial. If you are migrating from Chisel2, see [the migration guide](https://www.chisel-lang.org/chisel3/chisel3-vs-chisel2.html). -- cgit v1.2.3