From c6b34ead5878d2b8a64ea0a4b887e84fc39fff1d Mon Sep 17 00:00:00 2001 From: Sequencer Date: Sun, 24 Mar 2019 04:40:00 +0800 Subject: move doNotDedup to experimental (#1008) --- .../src/main/scala/chisel3/core/Annotation.scala | 50 +++++++++++++++++++++- src/main/scala/chisel3/package.scala | 1 + src/test/scala/chiselTests/AnnotationNoDedup.scala | 7 +-- 3 files changed, 51 insertions(+), 7 deletions(-) diff --git a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala index 93a02139..b2c9ea78 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Annotation.scala @@ -5,9 +5,10 @@ package chisel3.core import scala.language.existentials import chisel3.internal.{Builder, InstanceId} +import chisel3.core.ImplicitModule import firrtl.Transform import firrtl.annotations.{Annotation, CircuitName, ComponentName, ModuleName} -import firrtl.transforms.DontTouchAnnotation +import firrtl.transforms.{DontTouchAnnotation, NoDedupAnnotation} /** Interface for Annotations in Chisel * @@ -88,3 +89,50 @@ object dontTouch { // scalastyle:ignore object.name } } +/** Marks that a module to be ignored in Dedup Transform in Firrtl pass + * + * @example {{{ + * def fullAdder(a: UInt, b: UInt, myName: String): UInt = { + * val m = Module(new Module { + * val io = IO(new Bundle { + * val a = Input(UInt(32.W)) + * val b = Input(UInt(32.W)) + * val out = Output(UInt(32.W)) + * }) + * override def desiredName = s"adder_$myNname" + * io.out := io.a + io.b + * }) + * doNotDedup(m) + * m.io.a := a + * m.io.b := b + * m.io.out + * } + * + *class AdderTester extends Module + * with ConstantPropagationTest { + * val io = IO(new Bundle { + * val a = Input(UInt(32.W)) + * val b = Input(UInt(32.W)) + * val out = Output(Vec(2, UInt(32.W))) + * }) + * + * io.out(0) := fullAdder(io.a, io.b, "mod1") + * io.out(1) := fullAdder(io.a, io.b, "mod2") + * } + * }}} + * + * @note Calling this on [[Data]] creates an annotation that Chisel emits to a separate annotations + * file. This file must be passed to FIRRTL independently of the `.fir` file. The execute methods + * in [[chisel3.Driver]] will pass the annotations to FIRRTL automatically. + */ + +object doNotDedup { // scalastyle:ignore object.name + /** Marks a module to be ignored in Dedup Transform in Firrtl + * + * @param data The module to be marked + * @return Unmodified signal `module` + */ + def apply[T <: LegacyModule](module: T)(implicit compileOptions: CompileOptions): Unit = { + annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) }) + } +} diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index e75184db..02c4ecf5 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -437,6 +437,7 @@ package object chisel3 { // scalastyle:ignore package.object.name val withReset = chisel3.core.withReset val dontTouch = chisel3.core.dontTouch + val doNotDedup = chisel3.core.doNotDedup type BaseModule = chisel3.core.BaseModule type RawModule = chisel3.core.RawModule diff --git a/src/test/scala/chiselTests/AnnotationNoDedup.scala b/src/test/scala/chiselTests/AnnotationNoDedup.scala index 0f195fdf..d94cc2fc 100644 --- a/src/test/scala/chiselTests/AnnotationNoDedup.scala +++ b/src/test/scala/chiselTests/AnnotationNoDedup.scala @@ -3,16 +3,11 @@ package chiselTests import chisel3._ -import chisel3.experimental.{annotate, ChiselAnnotation} +import chisel3.experimental.{annotate, ChiselAnnotation, doNotDedup} import firrtl.FirrtlExecutionSuccess import firrtl.transforms.NoDedupAnnotation import org.scalatest.{FreeSpec, Matchers} -object doNotDedup { - def apply(module: Module): Unit = { - annotate(new ChiselAnnotation { def toFirrtl = NoDedupAnnotation(module.toNamed) }) - } -} class MuchUsedModule extends Module { val io = IO(new Bundle { -- cgit v1.2.3