From c2985aa6ef95a45d6ce9663a17f835eaba0cb9c5 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 5 Oct 2021 13:20:28 -0700
Subject: Fix naming of unwrapped val io in Chisel.Modules (#2150)

The removal of virtual method io accidentally made the naming of io in
compatibility mode Bundles sensitive to the prefix at the time of the
first access of the field. It also made .suggestName able to override
the name. This commit fixes that issue by forcing the name of the io
Data to be "io" no matter what.---
 core/src/main/scala/chisel3/RawModule.scala        |  2 +-
 core/src/main/scala/chisel3/internal/Builder.scala | 11 +++++++++
 src/test/scala/chiselTests/CompatibilitySpec.scala | 28 ++++++++++++++++++++++
 3 files changed, 40 insertions(+), 1 deletion(-)

diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index f1b4c1cf..c001772b 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -199,7 +199,7 @@ package object internal {
 
     tryJavaReflect
       .orElse(tryScalaReflect)
-      .map(_.autoSeed("io"))
+      .map(_.forceFinalName("io"))
       .orElse {
         // Fallback if reflection fails, user can wrap in IO(...)
         self.findPort("io")
diff --git a/core/src/main/scala/chisel3/internal/Builder.scala b/core/src/main/scala/chisel3/internal/Builder.scala
index 4e68623d..0a0a3f2d 100644
--- a/core/src/main/scala/chisel3/internal/Builder.scala
+++ b/core/src/main/scala/chisel3/internal/Builder.scala
@@ -154,6 +154,17 @@ private[chisel3] trait HasId extends InstanceId {
     this
   }
 
+  // Internal version of .suggestName that can override a user-suggested name
+  // This only exists for maintaining "val io" naming in compatibility-mode Modules without IO
+  // wrapping
+  private[chisel3] def forceFinalName(seed: String): this.type = {
+    // This could be called with user prefixes, ignore them
+    noPrefix {
+      suggested_seed = Some(seed)
+      this.suggestName(seed)
+    }
+  }
+
   /** Computes the name of this HasId, if one exists
     * @param defaultPrefix Optionally provide a default prefix for computing the name
     * @param defaultSeed Optionally provide default seed for computing the name
diff --git a/src/test/scala/chiselTests/CompatibilitySpec.scala b/src/test/scala/chiselTests/CompatibilitySpec.scala
index bf8cd3fc..ccf287a6 100644
--- a/src/test/scala/chiselTests/CompatibilitySpec.scala
+++ b/src/test/scala/chiselTests/CompatibilitySpec.scala
@@ -564,4 +564,32 @@ class CompatibiltySpec extends ChiselFlatSpec with ScalaCheckDrivenPropertyCheck
     verilog should include ("assign io_out_0 = io_in_0;")
   }
 
+  it should "ignore .suggestName on field io" in {
+    class MyModule extends Module {
+      val io = new Bundle {
+        val foo = UInt(width = 8).asInput
+        val bar = UInt(width = 8).asOutput
+      }
+      io.suggestName("potato")
+      io.bar := io.foo
+    }
+    val verilog = ChiselStage.emitVerilog(new MyModule)
+    verilog should include ("input  [7:0] io_foo")
+    verilog should include ("output [7:0] io_bar")
+  }
+
+  it should "properly name field io" in {
+    class MyModule extends Module {
+      val io = new Bundle {
+        val foo = UInt(width = 8).asInput
+        val bar = UInt(width = 8).asOutput
+      }
+      val wire = Wire(init = io.foo)
+      io.bar := wire
+    }
+    val verilog = ChiselStage.emitVerilog(new MyModule)
+    verilog should include ("input  [7:0] io_foo")
+    verilog should include ("output [7:0] io_bar")
+  }
+
 }
-- 
cgit v1.2.3