From bfee6b5183eb4d10599b91b7c68ce93be9577502 Mon Sep 17 00:00:00 2001 From: mergify[bot] Date: Wed, 22 Jun 2022 18:23:55 +0000 Subject: Replace verilog code with pre-formatted HTML to avoid breaking website (#2593) (#2599) (cherry picked from commit 6ecf4d39d413a7d955a8b358cb34685aaefed1a2) Co-authored-by: Carlos Eduardo --- README.md | 51 +++++++++++++++++++++++++-------------------------- 1 file changed, 25 insertions(+), 26 deletions(-) diff --git a/README.md b/README.md index a6c82d60..7c68145e 100644 --- a/README.md +++ b/README.md @@ -79,33 +79,32 @@ Should output the following Verilog:
Click to expand! -```verilog -module Blinky( - input clock, - input reset, - output io_led0 +
module Blinky(
+  input   clock,
+  input   reset,
+  output  io_led0
 );
-  reg  led; // @[main.scala 11:20]
-  reg [8:0] counterWrap_value; // @[Counter.scala 62:40]
-  wire  counterWrap_wrap_wrap = counterWrap_value == 9'h1f3; // @[Counter.scala 74:24]
-  wire [8:0] _counterWrap_wrap_value_T_1 = counterWrap_value + 9'h1; // @[Counter.scala 78:24]
-  assign io_led0 = led; // @[main.scala 16:11]
-  always @(posedge clock) begin
-    if (reset) begin // @[main.scala 11:20]
-      led <= 1'h0; // @[main.scala 11:20]
-    end else if (counterWrap_wrap_wrap) begin // @[main.scala 13:21]
-      led <= ~led; // @[main.scala 14:9]
-    end
-    if (reset) begin // @[Counter.scala 62:40]
-      counterWrap_value <= 9'h0; // @[Counter.scala 62:40]
-    end else if (counterWrap_wrap_wrap) begin // @[Counter.scala 88:20]
-      counterWrap_value <= 9'h0; // @[Counter.scala 88:28]
-    end else begin
-      counterWrap_value <= _counterWrap_wrap_value_T_1; // @[Counter.scala 78:15]
-    end
-  end
-endmodule
-```
+  reg  led; // @[main.scala 11:20]
+  reg [8:0] counterWrap_value; // @[Counter.scala 62:40]
+  wire  counterWrap_wrap_wrap = counterWrap_value == 9'h1f3; // @[Counter.scala 74:24]
+  wire [8:0] _counterWrap_wrap_value_T_1 = counterWrap_value + 9'h1; // @[Counter.scala 78:24]
+  assign io_led0 = led; // @[main.scala 16:11]
+  always @(posedge clock) begin
+    if (reset) begin // @[main.scala 11:20]
+      led <= 1'h0; // @[main.scala 11:20]
+    end else if (counterWrap_wrap_wrap) begin // @[main.scala 13:21]
+      led <= ~led; // @[main.scala 14:9]
+    end
+    if (reset) begin // @[Counter.scala 62:40]
+      counterWrap_value <= 9'h0; // @[Counter.scala 62:40]
+    end else if (counterWrap_wrap_wrap) begin // @[Counter.scala 88:20]
+      counterWrap_value <= 9'h0; // @[Counter.scala 88:28]
+    end else begin
+      counterWrap_value <= _counterWrap_wrap_value_T_1; // @[Counter.scala 78:15]
+    end
+  end
+endmodule
+
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