From bcad26c3fd9b9afdf9b27b0d489fec4e910d3d44 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Wed, 12 Feb 2020 14:59:56 -0800 Subject: Fix := of Reset and AsyncReset to DontCare (#1336) --- chiselFrontend/src/main/scala/chisel3/Bits.scala | 4 ++-- src/test/scala/chiselTests/AsyncResetSpec.scala | 22 ++++++++++++++++++++++ src/test/scala/chiselTests/ResetSpec.scala | 22 ++++++++++++++++++++++ 3 files changed, 46 insertions(+), 2 deletions(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala index 96eb74a4..43c34d9d 100644 --- a/chiselFrontend/src/main/scala/chisel3/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala @@ -989,7 +989,7 @@ final class ResetType(private[chisel3] val width: Width = Width(1)) extends Elem this.getClass == that.getClass override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { - case _: Reset => super.connect(that)(sourceInfo, connectCompileOptions) + case _: Reset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } @@ -1036,7 +1036,7 @@ sealed class AsyncReset(private[chisel3] val width: Width = Width(1)) extends El this.getClass == that.getClass override def connect(that: Data)(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions): Unit = that match { - case _: AsyncReset => super.connect(that)(sourceInfo, connectCompileOptions) + case _: AsyncReset | DontCare => super.connect(that)(sourceInfo, connectCompileOptions) case _ => super.badConnect(that)(sourceInfo) } diff --git a/src/test/scala/chiselTests/AsyncResetSpec.scala b/src/test/scala/chiselTests/AsyncResetSpec.scala index d2e04bf8..f602e9fb 100644 --- a/src/test/scala/chiselTests/AsyncResetSpec.scala +++ b/src/test/scala/chiselTests/AsyncResetSpec.scala @@ -119,10 +119,32 @@ class AsyncResetQueueTester extends BasicTester { } } +class AsyncResetDontCareModule extends RawModule { + import chisel3.util.Valid + val monoPort = IO(Output(AsyncReset())) + monoPort := DontCare + val monoWire = Wire(AsyncReset()) + monoWire := DontCare + val monoAggPort = IO(Output(Valid(AsyncReset()))) + monoAggPort := DontCare + val monoAggWire = Wire(Valid(AsyncReset())) + monoAggWire := DontCare + + // Can't bulk connect to Wire so only ports here + val bulkPort = IO(Output(AsyncReset())) + bulkPort <> DontCare + val bulkAggPort = IO(Output(Valid(AsyncReset()))) + bulkAggPort <> DontCare +} + class AsyncResetSpec extends ChiselFlatSpec { behavior of "AsyncReset" + it should "be able to be connected to DontCare" in { + elaborate(new AsyncResetDontCareModule) + } + it should "be allowed with literal reset values" in { elaborate(new BasicTester { withReset(reset.asAsyncReset)(RegInit(123.U)) diff --git a/src/test/scala/chiselTests/ResetSpec.scala b/src/test/scala/chiselTests/ResetSpec.scala index 2381aadc..2a17d52f 100644 --- a/src/test/scala/chiselTests/ResetSpec.scala +++ b/src/test/scala/chiselTests/ResetSpec.scala @@ -16,11 +16,33 @@ class ResetAgnosticModule extends RawModule { out := reg } +class AbstractResetDontCareModule extends RawModule { + import chisel3.util.Valid + val monoPort = IO(Output(Reset())) + monoPort := DontCare + val monoWire = Wire(Reset()) + monoWire := DontCare + val monoAggPort = IO(Output(Valid(Reset()))) + monoAggPort := DontCare + val monoAggWire = Wire(Valid(Reset())) + monoAggWire := DontCare + + // Can't bulk connect to Wire so only ports here + val bulkPort = IO(Output(Reset())) + bulkPort <> DontCare + val bulkAggPort = IO(Output(Valid(Reset()))) + bulkAggPort <> DontCare +} + class ResetSpec extends ChiselFlatSpec { behavior of "Reset" + it should "be able to be connected to DontCare" in { + elaborate(new AbstractResetDontCareModule) + } + it should "allow writing modules that are reset agnostic" in { val sync = compile(new Module { val io = IO(new Bundle { -- cgit v1.2.3