From ab083035655cbe1b1d73fc1d36db08cce8811fec Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Mon, 6 Feb 2017 18:12:26 -0800
Subject: Test that large Vecs can have widths inferred

Test for ucb-bar/firrtl#407
---
 src/test/scala/chiselTests/Vec.scala | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/src/test/scala/chiselTests/Vec.scala b/src/test/scala/chiselTests/Vec.scala
index 132bfcdc..e14ec3d9 100644
--- a/src/test/scala/chiselTests/Vec.scala
+++ b/src/test/scala/chiselTests/Vec.scala
@@ -109,6 +109,16 @@ class ShiftRegisterTester(n: Int) extends BasicTester {
   }
 }
 
+class HugeVecTester(n: Int) extends BasicTester {
+  require(n > 0)
+  val myVec = Wire(Vec(n, UInt()))
+  myVec.foreach { x =>
+    x := 123.U
+    assert(x === 123.U)
+  }
+  stop()
+}
+
 class VecSpec extends ChiselPropSpec {
   // Disable shrinking on error.
   implicit val noShrinkListVal = Shrink[List[Int]](_ => Stream.empty)
@@ -154,4 +164,8 @@ class VecSpec extends ChiselPropSpec {
   property("Regs of vecs should be usable as shift registers") {
     forAll(smallPosInts) { (n: Int) => assertTesterPasses{ new ShiftRegisterTester(n) } }
   }
+
+  property("Infering widths on huge Vecs should not cause a stack overflow") {
+    assertTesterPasses { new HugeVecTester(10000) }
+  }
 }
-- 
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