From 6a3eb3188c983268fab0f64ef4681b403cc2052d Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 28 Jan 2020 09:40:52 -0500 Subject: Emit FIRRTL andr, orr for Bits.{andR, orR} Change the emission strategy for Bits methods andR and orR to emit FIRRTL bitwise reduce operations andr and orr. Add two tests that assert the correct behavior of these operations in BitwiseOpsSpec. Signed-off-by: Schuyler Eldridge --- chiselFrontend/src/main/scala/chisel3/Bits.scala | 8 ++------ chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala | 2 ++ src/test/scala/chiselTests/BitwiseOps.scala | 2 ++ 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala index 57ce98d2..96eb74a4 100644 --- a/chiselFrontend/src/main/scala/chisel3/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala @@ -581,13 +581,9 @@ sealed class UInt private[chisel3] (width: Width) extends Bits(width) with Num[U final def xorR(): Bool = macro SourceInfoTransform.noArg /** @group SourceInfoTransformMacro */ - def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = this =/= 0.U + def do_orR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, OrReduceOp) /** @group SourceInfoTransformMacro */ - def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = width match { - // Generate a simpler expression if the width is known - case KnownWidth(w) => this === ((BigInt(1) << w) - 1).U - case UnknownWidth() => ~this === 0.U - } + def do_andR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, AndReduceOp) /** @group SourceInfoTransformMacro */ def do_xorR(implicit sourceInfo: SourceInfo, compileOptions: CompileOptions): Bool = redop(sourceInfo, XorReduceOp) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index a16d84bb..d98bebcd 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -47,6 +47,8 @@ object PrimOp { val NotEqualOp = PrimOp("neq") val NegOp = PrimOp("neg") val MultiplexOp = PrimOp("mux") + val AndReduceOp = PrimOp("andr") + val OrReduceOp = PrimOp("orr") val XorReduceOp = PrimOp("xorr") val ConvertOp = PrimOp("cvt") val AsUIntOp = PrimOp("asUInt") diff --git a/src/test/scala/chiselTests/BitwiseOps.scala b/src/test/scala/chiselTests/BitwiseOps.scala index 505178a4..20e3f01a 100644 --- a/src/test/scala/chiselTests/BitwiseOps.scala +++ b/src/test/scala/chiselTests/BitwiseOps.scala @@ -13,6 +13,8 @@ class BitwiseOpsTester(w: Int, _a: Int, _b: Int) extends BasicTester { assert((a & b) === (_a & _b).asUInt) assert((a | b) === (_a | _b).asUInt) assert((a ^ b) === (_a ^ _b).asUInt) + assert((a.orR) === (_a != 0).asBool) + assert((a.andR) === (s"%${w}s".format(BigInt(_a).toString(2)).foldLeft(true)(_ && _ == '1') ).asBool) stop() } -- cgit v1.2.3