From 9e992816e570284193e121cd9c24503fd8cb4427 Mon Sep 17 00:00:00 2001 From: Richard Lin Date: Mon, 21 Jan 2019 16:24:43 -0800 Subject: Unify internal (chisel3.core) and external (chisel3 / chisel3.experimental) Module class names (#994) --- .../src/main/scala/chisel3/core/Attach.scala | 2 +- .../src/main/scala/chisel3/core/BiConnect.scala | 8 +- .../src/main/scala/chisel3/core/Binding.scala | 8 +- .../src/main/scala/chisel3/core/Bits.scala | 2 +- .../src/main/scala/chisel3/core/MonoConnect.scala | 4 +- .../src/main/scala/chisel3/core/RawModule.scala | 235 +++++++++++++++++++++ .../src/main/scala/chisel3/core/UserModule.scala | 232 -------------------- .../src/main/scala/chisel3/internal/Builder.scala | 6 +- .../main/scala/chisel3/internal/firrtl/IR.scala | 2 +- .../scala/chisel3/internal/firrtl/Emitter.scala | 2 +- src/main/scala/chisel3/package.scala | 4 +- src/main/scala/chisel3/util/Decoupled.scala | 2 +- 12 files changed, 255 insertions(+), 252 deletions(-) create mode 100644 chiselFrontend/src/main/scala/chisel3/core/RawModule.scala delete mode 100644 chiselFrontend/src/main/scala/chisel3/core/UserModule.scala diff --git a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala index b3096fd5..8cb58f1c 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Attach.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Attach.scala @@ -14,7 +14,7 @@ object attach { // scalastyle:ignore object.name AttachException(": Conditional attach is not allowed!") // Actual implementation - private[core] def impl(elts: Seq[Analog], contextModule: UserModule)(implicit sourceInfo: SourceInfo): Unit = { + private[core] def impl(elts: Seq[Analog], contextModule: RawModule)(implicit sourceInfo: SourceInfo): Unit = { if (Builder.whenDepth != 0) throw ConditionalAttachException // TODO Check that references are valid and can be attached diff --git a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala index ad7ba98a..897ccacf 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/BiConnect.scala @@ -55,7 +55,7 @@ object BiConnect { * during the recursive decent and then rethrow them with extra information added. * This gives the user a 'path' to where in the connections things went wrong. */ - def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: UserModule): Unit = { + def connect(sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Data, right: Data, context_mod: RawModule): Unit = { (left, right) match { // Handle element case (root case) case (left_a: Analog, right_a: Analog) => @@ -154,7 +154,7 @@ object BiConnect { connectCompileOptions: CompileOptions, left_r: Record, right_r: Record, - context_mod: UserModule): Unit = { + context_mod: RawModule): Unit = { // Verify right has no extra fields that left doesn't have for((field, right_sub) <- right_r.elements) { if(!left_r.elements.isDefinedAt(field)) { @@ -207,7 +207,7 @@ object BiConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: UserModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, left: Element, right: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If left or right have no location, assume in context module // This can occur if one of them is a literal, unbound will error previously @@ -313,7 +313,7 @@ object BiConnect { // This function checks if analog element-level attaching is allowed // Then it either issues it or throws the appropriate exception. - def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: UserModule): Unit = { + def analogAttach(implicit sourceInfo: SourceInfo, left: Analog, right: Analog, contextModule: RawModule): Unit = { // Error if left or right is BICONNECTED in the current module already for (elt <- left :: right :: Nil) { elt.biConnectLocs.get(contextModule) match { diff --git a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala index 60235477..4c352bc6 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Binding.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Binding.scala @@ -96,11 +96,11 @@ sealed trait ReadOnlyBinding extends TopBinding // TODO(twigg): Ops between unenclosed nodes can also be unenclosed // However, Chisel currently binds all op results to a module -case class OpBinding(enclosure: UserModule) extends ConstrainedBinding with ReadOnlyBinding -case class MemoryPortBinding(enclosure: UserModule) extends ConstrainedBinding +case class OpBinding(enclosure: RawModule) extends ConstrainedBinding with ReadOnlyBinding +case class MemoryPortBinding(enclosure: RawModule) extends ConstrainedBinding case class PortBinding(enclosure: BaseModule) extends ConstrainedBinding -case class RegBinding(enclosure: UserModule) extends ConstrainedBinding -case class WireBinding(enclosure: UserModule) extends ConstrainedBinding +case class RegBinding(enclosure: RawModule) extends ConstrainedBinding +case class WireBinding(enclosure: RawModule) extends ConstrainedBinding case class ChildBinding(parent: Data) extends Binding { def location = parent.topBinding.location diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala index abc7b583..83c8637a 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala @@ -1734,7 +1734,7 @@ final class Analog private (private[chisel3] val width: Width) extends Element { // Used to enforce single bulk connect of Analog types, multi-attach is still okay // Note that this really means 1 bulk connect per Module because a port can // be connected in the parent module as well - private[core] val biConnectLocs = mutable.Map.empty[UserModule, SourceInfo] + private[core] val biConnectLocs = mutable.Map.empty[RawModule, SourceInfo] // Define setter/getter pairing // Analog can only be bound to Ports and Wires (and Unbound) diff --git a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala index d4c80405..0773c7a2 100644 --- a/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala +++ b/chiselFrontend/src/main/scala/chisel3/core/MonoConnect.scala @@ -64,7 +64,7 @@ object MonoConnect { connectCompileOptions: CompileOptions, sink: Data, source: Data, - context_mod: UserModule): Unit = + context_mod: RawModule): Unit = (sink, source) match { // Handle legal element cases, note (Bool, Bool) is caught by the first two, as Bool is a UInt @@ -157,7 +157,7 @@ object MonoConnect { // This function checks if element-level connection operation allowed. // Then it either issues it or throws the appropriate exception. - def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: UserModule): Unit = { + def elemConnect(implicit sourceInfo: SourceInfo, connectCompileOptions: CompileOptions, sink: Element, source: Element, context_mod: RawModule): Unit = { import BindingDirection.{Internal, Input, Output} // Using extensively so import these // If source has no location, assume in context module // This can occur if is a literal, unbound will error previously diff --git a/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala new file mode 100644 index 00000000..1a9911e6 --- /dev/null +++ b/chiselFrontend/src/main/scala/chisel3/core/RawModule.scala @@ -0,0 +1,235 @@ +// See LICENSE for license details. + +package chisel3.core + +import scala.collection.mutable.{ArrayBuffer, HashMap} +import scala.collection.JavaConversions._ +import scala.language.experimental.macros + +import chisel3.internal._ +import chisel3.internal.Builder._ +import chisel3.internal.firrtl._ +import chisel3.internal.firrtl.{Command => _, _} +import chisel3.internal.sourceinfo.UnlocatableSourceInfo + +/** Abstract base class for Modules that contain Chisel RTL. + * This abstract base class is a user-defined module which does not include implicit clock and reset and supports + * multiple IO() declarations. + */ +abstract class RawModule(implicit moduleCompileOptions: CompileOptions) + extends BaseModule { + // + // RTL construction internals + // + private val _commands = ArrayBuffer[Command]() + private[chisel3] def addCommand(c: Command) { + require(!_closed, "Can't write to module after module close") + _commands += c + } + protected def getCommands = { + require(_closed, "Can't get commands before module close") + _commands.toSeq + } + + // + // Other Internal Functions + // + // For debuggers/testers, TODO: refactor out into proper public API + private var _firrtlPorts: Option[Seq[firrtl.Port]] = None + lazy val getPorts = _firrtlPorts.get + + val compileOptions = moduleCompileOptions + + private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { + for (port <- getModulePorts) { + port.suggestedName.orElse(names.get(port)) match { + case Some(name) => + if (_namespace.contains(name)) { + Builder.error(s"""Unable to name port $port to "$name" in $this,""" + + " name is already taken by another port!") + } + port.setRef(ModuleIO(this, _namespace.name(name))) + case None => Builder.error(s"Unable to name port $port in $this, " + + "try making it a public field of the Module") + } + } + } + + + private[core] override def generateComponent(): Component = { + require(!_closed, "Can't generate module more than once") + _closed = true + + val names = nameIds(classOf[RawModule]) + + // Ports get first naming priority, since they are part of a Module's IO spec + namePorts(names) + + // Then everything else gets named + for ((node, name) <- names) { + node.suggestName(name) + } + + // All suggestions are in, force names to every node. + for (id <- getIds) { + id match { + case id: BaseModule => id.forceName(default=id.desiredName, _namespace) + case id: MemBase[_] => id.forceName(default="_T", _namespace) + case id: Data if id.topBindingOpt.isDefined => id.topBinding match { + case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) => + id.forceName(default="_T", _namespace) + case _ => // don't name literals + } + case id: Data if id.topBindingOpt.isEmpty => // don't name unbound types + } + id._onModuleClose + } + + val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)} + _firrtlPorts = Some(firrtlPorts) + + // Generate IO invalidation commands to initialize outputs as unused, + // unless the client wants explicit control over their generation. + val invalidateCommands = { + if (!compileOptions.explicitInvalidate) { + getModulePorts map { port => DefInvalid(UnlocatableSourceInfo, port.ref) } + } else { + Seq() + } + } + val component = DefModule(this, name, firrtlPorts, invalidateCommands ++ getCommands) + _component = Some(component) + component + } + + private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = { + implicit val sourceInfo = UnlocatableSourceInfo + + if (!parentCompileOptions.explicitInvalidate) { + for (port <- getModulePorts) { + pushCommand(DefInvalid(sourceInfo, port.ref)) + } + } + } +} + +/** Abstract base class for Modules, which behave much like Verilog modules. + * These may contain both logic and state which are written in the Module + * body (constructor). + * This abstract base class includes an implicit clock and reset. + * + * @note Module instantiations must be wrapped in a Module() call. + */ +abstract class MultiIOModule(implicit moduleCompileOptions: CompileOptions) + extends RawModule { + // Implicit clock and reset pins + val clock: Clock = IO(Input(Clock())) + val reset: Reset = IO(Input(Bool())) + + // Setup ClockAndReset + Builder.currentClockAndReset = Some(ClockAndReset(clock, reset)) + + private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { + implicit val sourceInfo = UnlocatableSourceInfo + + super.initializeInParent(parentCompileOptions) + clock := Builder.forcedClock + reset := Builder.forcedReset + } +} + +/** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor + * for threading through explicit clock and reset. + * + * While this class isn't planned to be removed anytime soon (there are benefits to restricting + * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module + * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins. + */ +abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) + extends MultiIOModule { + // These are to be phased out + protected var override_clock: Option[Clock] = None + protected var override_reset: Option[Bool] = None + + // _clock and _reset can be clock and reset in these 2ary constructors + // once chisel2 compatibility issues are resolved + @chiselRuntimeDeprecated + @deprecated("Module constructor with override_clock and override_reset deprecated, use withClockAndReset", "chisel3") + def this(override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) + (implicit moduleCompileOptions: CompileOptions) = { + this() + this.override_clock = override_clock + this.override_reset = override_reset + } + + @chiselRuntimeDeprecated + @deprecated("Module constructor with override _clock deprecated, use withClock", "chisel3") + def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) + + @chiselRuntimeDeprecated + @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3") + def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) + + @chiselRuntimeDeprecated + @deprecated("Module constructor with override _clock, _reset deprecated, use withClockAndReset", "chisel3") + def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) + + // IO for this Module. At the Scala level (pre-FIRRTL transformations), + // connections in and out of a Module may only go through `io` elements. + def io: Record + + // Allow access to bindings from the compatibility package + protected def _compatIoPortBound() = portsContains(io) + + protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { + val names = super.nameIds(rootClass) + + // Allow IO naming without reflection + names.put(io, "io") + names.put(clock, "clock") + names.put(reset, "reset") + + names + } + + private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { + for (port <- getModulePorts) { + // This should already have been caught + if (!names.contains(port)) throwException(s"Unable to name port $port in $this") + val name = names(port) + port.setRef(ModuleIO(this, _namespace.name(name))) + } + } + + private[core] override def generateComponent(): Component = { + _compatAutoWrapPorts() // pre-IO(...) compatibility hack + + // Restrict IO to just io, clock, and reset + require(io != null, "Module must have io") + require(portsContains(io), "Module must have io wrapped in IO(...)") + require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") + require(portsSize == 3, "Module must only have io, clock, and reset as IO") + + super.generateComponent() + } + + private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { + // Don't generate source info referencing parents inside a module, since this interferes with + // module de-duplication in FIRRTL emission. + implicit val sourceInfo = UnlocatableSourceInfo + + if (!parentCompileOptions.explicitInvalidate) { + pushCommand(DefInvalid(sourceInfo, io.ref)) + } + + override_clock match { + case Some(override_clock) => clock := override_clock + case _ => clock := Builder.forcedClock + } + + override_reset match { + case Some(override_reset) => reset := override_reset + case _ => reset := Builder.forcedReset + } + } +} diff --git a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala b/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala deleted file mode 100644 index 5183f860..00000000 --- a/chiselFrontend/src/main/scala/chisel3/core/UserModule.scala +++ /dev/null @@ -1,232 +0,0 @@ -// See LICENSE for license details. - -package chisel3.core - -import scala.collection.mutable.{ArrayBuffer, HashMap} -import scala.collection.JavaConversions._ -import scala.language.experimental.macros - -import chisel3.internal._ -import chisel3.internal.Builder._ -import chisel3.internal.firrtl._ -import chisel3.internal.firrtl.{Command => _, _} -import chisel3.internal.sourceinfo.UnlocatableSourceInfo - -/** Abstract base class for Modules that contain Chisel RTL. - */ -abstract class UserModule(implicit moduleCompileOptions: CompileOptions) - extends BaseModule { - // - // RTL construction internals - // - private val _commands = ArrayBuffer[Command]() - private[chisel3] def addCommand(c: Command) { - require(!_closed, "Can't write to module after module close") - _commands += c - } - protected def getCommands = { - require(_closed, "Can't get commands before module close") - _commands.toSeq - } - - // - // Other Internal Functions - // - // For debuggers/testers, TODO: refactor out into proper public API - private var _firrtlPorts: Option[Seq[firrtl.Port]] = None - lazy val getPorts = _firrtlPorts.get - - val compileOptions = moduleCompileOptions - - private[chisel3] def namePorts(names: HashMap[HasId, String]): Unit = { - for (port <- getModulePorts) { - port.suggestedName.orElse(names.get(port)) match { - case Some(name) => - if (_namespace.contains(name)) { - Builder.error(s"""Unable to name port $port to "$name" in $this,""" + - " name is already taken by another port!") - } - port.setRef(ModuleIO(this, _namespace.name(name))) - case None => Builder.error(s"Unable to name port $port in $this, " + - "try making it a public field of the Module") - } - } - } - - - private[core] override def generateComponent(): Component = { - require(!_closed, "Can't generate module more than once") - _closed = true - - val names = nameIds(classOf[UserModule]) - - // Ports get first naming priority, since they are part of a Module's IO spec - namePorts(names) - - // Then everything else gets named - for ((node, name) <- names) { - node.suggestName(name) - } - - // All suggestions are in, force names to every node. - for (id <- getIds) { - id match { - case id: BaseModule => id.forceName(default=id.desiredName, _namespace) - case id: MemBase[_] => id.forceName(default="_T", _namespace) - case id: Data if id.topBindingOpt.isDefined => id.topBinding match { - case OpBinding(_) | MemoryPortBinding(_) | PortBinding(_) | RegBinding(_) | WireBinding(_) => - id.forceName(default="_T", _namespace) - case _ => // don't name literals - } - case id: Data if id.topBindingOpt.isEmpty => // don't name unbound types - } - id._onModuleClose - } - - val firrtlPorts = getModulePorts map {port => Port(port, port.specifiedDirection)} - _firrtlPorts = Some(firrtlPorts) - - // Generate IO invalidation commands to initialize outputs as unused, - // unless the client wants explicit control over their generation. - val invalidateCommands = { - if (!compileOptions.explicitInvalidate) { - getModulePorts map { port => DefInvalid(UnlocatableSourceInfo, port.ref) } - } else { - Seq() - } - } - val component = DefModule(this, name, firrtlPorts, invalidateCommands ++ getCommands) - _component = Some(component) - component - } - - private[core] def initializeInParent(parentCompileOptions: CompileOptions): Unit = { - implicit val sourceInfo = UnlocatableSourceInfo - - if (!parentCompileOptions.explicitInvalidate) { - for (port <- getModulePorts) { - pushCommand(DefInvalid(sourceInfo, port.ref)) - } - } - } -} - -/** Abstract base class for Modules, which behave much like Verilog modules. - * These may contain both logic and state which are written in the Module - * body (constructor). - * - * @note Module instantiations must be wrapped in a Module() call. - */ -abstract class ImplicitModule(implicit moduleCompileOptions: CompileOptions) - extends UserModule { - // Implicit clock and reset pins - val clock: Clock = IO(Input(Clock())) - val reset: Reset = IO(Input(Bool())) - - // Setup ClockAndReset - Builder.currentClockAndReset = Some(ClockAndReset(clock, reset)) - - private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { - implicit val sourceInfo = UnlocatableSourceInfo - - super.initializeInParent(parentCompileOptions) - clock := Builder.forcedClock - reset := Builder.forcedReset - } -} - -/** Legacy Module class that restricts IOs to just io, clock, and reset, and provides a constructor - * for threading through explicit clock and reset. - * - * While this class isn't planned to be removed anytime soon (there are benefits to restricting - * IO), the clock and reset constructors will be phased out. Recommendation is to wrap the module - * in a withClock/withReset/withClockAndReset block, or directly hook up clock or reset IO pins. - */ -abstract class LegacyModule(implicit moduleCompileOptions: CompileOptions) - extends ImplicitModule { - // These are to be phased out - protected var override_clock: Option[Clock] = None - protected var override_reset: Option[Bool] = None - - // _clock and _reset can be clock and reset in these 2ary constructors - // once chisel2 compatibility issues are resolved - @chiselRuntimeDeprecated - @deprecated("Module constructor with override_clock and override_reset deprecated, use withClockAndReset", "chisel3") - def this(override_clock: Option[Clock]=None, override_reset: Option[Bool]=None) - (implicit moduleCompileOptions: CompileOptions) = { - this() - this.override_clock = override_clock - this.override_reset = override_reset - } - - @chiselRuntimeDeprecated - @deprecated("Module constructor with override _clock deprecated, use withClock", "chisel3") - def this(_clock: Clock)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), None)(moduleCompileOptions) - - @chiselRuntimeDeprecated - @deprecated("Module constructor with override _reset deprecated, use withReset", "chisel3") - def this(_reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(None, Option(_reset))(moduleCompileOptions) - - @chiselRuntimeDeprecated - @deprecated("Module constructor with override _clock, _reset deprecated, use withClockAndReset", "chisel3") - def this(_clock: Clock, _reset: Bool)(implicit moduleCompileOptions: CompileOptions) = this(Option(_clock), Option(_reset))(moduleCompileOptions) - - // IO for this Module. At the Scala level (pre-FIRRTL transformations), - // connections in and out of a Module may only go through `io` elements. - def io: Record - - // Allow access to bindings from the compatibility package - protected def _compatIoPortBound() = portsContains(io) - - protected override def nameIds(rootClass: Class[_]): HashMap[HasId, String] = { - val names = super.nameIds(rootClass) - - // Allow IO naming without reflection - names.put(io, "io") - names.put(clock, "clock") - names.put(reset, "reset") - - names - } - - private[chisel3] override def namePorts(names: HashMap[HasId, String]): Unit = { - for (port <- getModulePorts) { - // This should already have been caught - if (!names.contains(port)) throwException(s"Unable to name port $port in $this") - val name = names(port) - port.setRef(ModuleIO(this, _namespace.name(name))) - } - } - - private[core] override def generateComponent(): Component = { - _compatAutoWrapPorts() // pre-IO(...) compatibility hack - - // Restrict IO to just io, clock, and reset - require(io != null, "Module must have io") - require(portsContains(io), "Module must have io wrapped in IO(...)") - require((portsContains(clock)) && (portsContains(reset)), "Internal error, module did not have clock or reset as IO") - require(portsSize == 3, "Module must only have io, clock, and reset as IO") - - super.generateComponent() - } - - private[core] override def initializeInParent(parentCompileOptions: CompileOptions): Unit = { - // Don't generate source info referencing parents inside a module, since this interferes with - // module de-duplication in FIRRTL emission. - implicit val sourceInfo = UnlocatableSourceInfo - - if (!parentCompileOptions.explicitInvalidate) { - pushCommand(DefInvalid(sourceInfo, io.ref)) - } - - override_clock match { - case Some(override_clock) => clock := override_clock - case _ => clock := Builder.forcedClock - } - - override_reset match { - case Some(override_reset) => reset := override_reset - case _ => reset := Builder.forcedReset - } - } -} diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index 0938ea9e..f0bb5605 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -222,8 +222,8 @@ private[chisel3] object Builder { // A bare api call is, e.g. calling Wire() from the scala console). ) } - def forcedUserModule: UserModule = currentModule match { - case Some(module: UserModule) => module + def forcedUserModule: RawModule = currentModule match { + case Some(module: RawModule) => module case _ => throwException( "Error: Not in a UserModule. Likely cause: Missed Module() wrap, bare chisel API call, or attempting to construct hardware inside a BlackBox." // A bare api call is, e.g. calling Wire() from the scala console). @@ -325,7 +325,7 @@ private[chisel3] object Builder { throwException(m) } - def build[T <: UserModule](f: => T): Circuit = { + def build[T <: RawModule](f: => T): Circuit = { chiselContext.withValue(new ChiselContext) { dynamicContextVar.withValue(Some(new DynamicContext())) { errors.info("Elaborating design...") diff --git a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala index ae8b248a..c05d402d 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/firrtl/IR.scala @@ -286,7 +286,7 @@ abstract class Component extends Arg { def name: String def ports: Seq[Port] } -case class DefModule(id: UserModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component +case class DefModule(id: RawModule, name: String, ports: Seq[Port], commands: Seq[Command]) extends Component case class DefBlackBox(id: BaseBlackBox, name: String, ports: Seq[Port], topDir: SpecifiedDirection, params: Map[String, Param]) extends Component case class Circuit(name: String, components: Seq[Component], annotations: Seq[ChiselAnnotation] = Seq.empty) diff --git a/src/main/scala/chisel3/internal/firrtl/Emitter.scala b/src/main/scala/chisel3/internal/firrtl/Emitter.scala index ac4bf8e7..68513423 100644 --- a/src/main/scala/chisel3/internal/firrtl/Emitter.scala +++ b/src/main/scala/chisel3/internal/firrtl/Emitter.scala @@ -110,7 +110,7 @@ private class Emitter(circuit: Circuit) { */ private def moduleDecl(m: Component): String = m.id match { case _: chisel3.core.BaseBlackBox => newline + s"extmodule ${m.name} : " - case _: chisel3.core.UserModule => newline + s"module ${m.name} : " + case _: chisel3.core.RawModule => newline + s"module ${m.name} : " } /** Generates the FIRRTL module definition. diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala index e79a1186..3b1275f6 100644 --- a/src/main/scala/chisel3/package.scala +++ b/src/main/scala/chisel3/package.scala @@ -430,8 +430,8 @@ package object chisel3 { // scalastyle:ignore package.object.name val dontTouch = chisel3.core.dontTouch type BaseModule = chisel3.core.BaseModule - type MultiIOModule = chisel3.core.ImplicitModule - type RawModule = chisel3.core.UserModule + type RawModule = chisel3.core.RawModule + type MultiIOModule = chisel3.core.MultiIOModule type ExtModule = chisel3.core.ExtModule val IO = chisel3.core.IO diff --git a/src/main/scala/chisel3/util/Decoupled.scala b/src/main/scala/chisel3/util/Decoupled.scala index d2a6552d..c3c0d224 100644 --- a/src/main/scala/chisel3/util/Decoupled.scala +++ b/src/main/scala/chisel3/util/Decoupled.scala @@ -21,7 +21,7 @@ abstract class ReadyValidIO[+T <: Data](gen: T) extends Bundle { // Compatibility hack for rocket-chip private val genType = (DataMirror.internal.isSynthesizable(gen), chisel3.internal.Builder.currentModule) match { - case (true, Some(module: chisel3.core.ImplicitModule)) + case (true, Some(module: chisel3.core.MultiIOModule)) if !module.compileOptions.declaredTypeMustBeUnbound => chiselTypeOf(gen) case _ => gen } -- cgit v1.2.3