From 9a259303f684091c3bc313d47c6727af2f4da6aa Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Wed, 31 Jul 2019 08:46:32 -0700
Subject: Fix shift register in README

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index ed7d6bcd..81e4788c 100644
--- a/README.md
+++ b/README.md
@@ -46,7 +46,7 @@ class FirFilter(bitWidth: Int, coeffs: Seq[UInt]) extends Module {
     val out = Output(UInt(bitWidth.W))
   })
   // Create the serial-in, parallel-out shift register
-  val zs = Wire(Vec(coeffs.length, UInt(bitWidth.W)))
+  val zs = Reg(Vec(coeffs.length, UInt(bitWidth.W)))
   zs(0) := io.in
   for (i <- 1 until coeffs.length) {
     zs(i) := zs(i-1)
-- 
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