From fc472186d88b33a48bb7440396ed6a9da8485b1d Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Wed, 25 Sep 2019 16:23:08 -0400
Subject: Use raw link for FIR filter

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index f4c70ae3..9318608d 100644
--- a/README.md
+++ b/README.md
@@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt
 
 Consider an FIR filter that implements a convolution operation, as depicted in this block diagram:
 
-<img src="https://github.com/freechipsproject/chisel3/blob/readme-fix/doc/images/fir_filter.svg?sanitize=true" width="512" />
+<img src="https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/fir_filter.svg?sanitize=true" width="512" />
 
 While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such:
 
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