From 917ef93d6add8dabebccb31e7768a887609f6502 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 29 Jul 2015 00:38:53 -0700
Subject: Fix Bundle port ordering

---
 src/main/scala/Chisel/Core.scala | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/main/scala/Chisel/Core.scala b/src/main/scala/Chisel/Core.scala
index 64c0e0f6..37f1f35a 100644
--- a/src/main/scala/Chisel/Core.scala
+++ b/src/main/scala/Chisel/Core.scala
@@ -936,7 +936,7 @@ object Bundle {
 
 class Bundle(dirArg: Direction = NO_DIR) extends Aggregate(dirArg) { 
   def toPorts: Seq[Port] =
-    elements.map(_._2.toPort).toSeq
+    elements.map(_._2.toPort).toSeq.reverse
   def toType: BundleType = 
     BundleType(this.toPorts, isFlipVar)
 
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