From 8e15bd90e179be15145ca3b04b8a4498fc0a9b73 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Fri, 18 Mar 2016 01:02:56 -0700
Subject: Only randomize directory names during testing

---
 src/main/scala/Chisel/testers/TesterDriver.scala | 11 +++++------
 src/test/scala/chiselTests/Harness.scala         | 23 +++++++++++------------
 2 files changed, 16 insertions(+), 18 deletions(-)

diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala
index 4547f48f..c0cdfb3f 100644
--- a/src/main/scala/Chisel/testers/TesterDriver.scala
+++ b/src/main/scala/Chisel/testers/TesterDriver.scala
@@ -30,8 +30,7 @@ object TesterDriver extends BackendCompilationUtilities {
     val target = circuit.name
 
     val path = createTempDirectory(target)
-    val fname = File.createTempFile(target, "", path)
-    val prefix = fname.toString.split("/").last
+    val fname = new File(path, target)
 
     // For now, dump the IR out to a file
     Driver.dumpFirrtl(circuit, Some(new File(fname.toString + ".fir")))
@@ -47,10 +46,10 @@ object TesterDriver extends BackendCompilationUtilities {
     })
 
     // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe
-    if ((firrtlToVerilog(prefix, path) #&&
-        verilogToCpp(prefix, path, additionalVFiles, cppHarness) #&&
-        cppToExe(prefix, path)).! == 0) {
-      executeExpectingSuccess(prefix, path)
+    if ((firrtlToVerilog(target, path) #&&
+        verilogToCpp(target, path, additionalVFiles, cppHarness) #&&
+        cppToExe(target, path)).! == 0) {
+      executeExpectingSuccess(target, path)
     } else {
       false
     }
diff --git a/src/test/scala/chiselTests/Harness.scala b/src/test/scala/chiselTests/Harness.scala
index 1a628e6c..b06f4572 100644
--- a/src/test/scala/chiselTests/Harness.scala
+++ b/src/test/scala/chiselTests/Harness.scala
@@ -50,30 +50,29 @@ int main(int argc, char **argv, char **env) {
   def simpleHarnessBackend(make: File => File): (File, String) = {
     val target = "test"
     val path = createTempDirectory(target)
-    val fname = File.createTempFile(target, "", path)
-    val prefix = fname.toString.split("/").last
+    val fname = new File(path, target)
 
     val cppHarness = makeCppHarness(fname)
 
     make(fname)
-    verilogToCpp(prefix, path, Seq(), cppHarness).!
-    cppToExe(prefix, path).!
-    (path, prefix)
+    verilogToCpp(target, path, Seq(), cppHarness).!
+    cppToExe(target, path).!
+    (path, target)
   }
 
   property("Test making trivial verilog harness and executing") {
-    val (path, prefix) = simpleHarnessBackend(makeTrivialVerilog)
+    val (path, target) = simpleHarnessBackend(makeTrivialVerilog)
 
-    assert(executeExpectingSuccess(prefix, path))
+    assert(executeExpectingSuccess(target, path))
   }
 
   property("Test that assertion failues in Verilog are caught") {
-    val (path, prefix) = simpleHarnessBackend(makeFailingVerilog)
+    val (path, target) = simpleHarnessBackend(makeFailingVerilog)
 
-    assert(!executeExpectingSuccess(prefix, path))
-    assert(executeExpectingFailure(prefix, path))
-    assert(executeExpectingFailure(prefix, path, "My specific, expected error message!"))
-    assert(!executeExpectingFailure(prefix, path, "A string that doesn't match any test output"))
+    assert(!executeExpectingSuccess(target, path))
+    assert(executeExpectingFailure(target, path))
+    assert(executeExpectingFailure(target, path, "My specific, expected error message!"))
+    assert(!executeExpectingFailure(target, path, "A string that doesn't match any test output"))
   }
 }
 
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