From 8baa2ab806be1aa85a7a1da7b348726da1bd1d19 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Thu, 11 May 2017 15:07:30 -0700 Subject: Scope resources - move them down into chisel3 directory - fixes #549 (#610) --- src/main/resources/Makefile | 35 -------- src/main/resources/chisel3/Makefile | 35 ++++++++ src/main/resources/chisel3/top.cpp | 95 ++++++++++++++++++++++ src/main/resources/top.cpp | 95 ---------------------- src/main/scala/chisel3/testers/TesterDriver.scala | 2 +- src/test/resources/AnalogBlackBox.v | 27 ------ src/test/resources/BlackBoxTest.v | 67 --------------- src/test/resources/VerilogVendingMachine.v | 44 ---------- src/test/resources/chisel3/AnalogBlackBox.v | 27 ++++++ src/test/resources/chisel3/BlackBoxTest.v | 67 +++++++++++++++ src/test/resources/chisel3/VerilogVendingMachine.v | 44 ++++++++++ .../scala/chiselTests/AnalogIntegrationSpec.scala | 4 +- src/test/scala/chiselTests/AnalogSpec.scala | 14 ++-- src/test/scala/chiselTests/BlackBox.scala | 8 +- src/test/scala/chiselTests/BlackBoxImpl.scala | 2 +- src/test/scala/chiselTests/ExtModule.scala | 4 +- src/test/scala/examples/SimpleVendingMachine.scala | 2 +- 17 files changed, 286 insertions(+), 286 deletions(-) delete mode 100644 src/main/resources/Makefile create mode 100644 src/main/resources/chisel3/Makefile create mode 100644 src/main/resources/chisel3/top.cpp delete mode 100644 src/main/resources/top.cpp delete mode 100644 src/test/resources/AnalogBlackBox.v delete mode 100644 src/test/resources/BlackBoxTest.v delete mode 100644 src/test/resources/VerilogVendingMachine.v create mode 100644 src/test/resources/chisel3/AnalogBlackBox.v create mode 100644 src/test/resources/chisel3/BlackBoxTest.v create mode 100644 src/test/resources/chisel3/VerilogVendingMachine.v diff --git a/src/main/resources/Makefile b/src/main/resources/Makefile deleted file mode 100644 index 221179a3..00000000 --- a/src/main/resources/Makefile +++ /dev/null @@ -1,35 +0,0 @@ -# Chisel parallel make template. - -HFILES = @HFILES@ -ONCEONLY = @ONCEONLY@ -UNOPTIMIZED = @UNOPTIMIZED@ -OPTIMIZED = @OPTIMIZED@ - -EXEC = @EXEC@ -OPTIM0 = @OPTIM0@ -OPTIM1 = @OPTIM1@ -OPTIM2 = @OPTIM2@ -CPPFLAGS = @CPPFLAGS@ -CXXFLAGS = @CXXFLAGS@ -LDFLAGS = @LDFLAGS@ -CXX = @CXX@ - -default: $(EXEC) - -clean: - $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) - -$(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) - -$(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile - $(CXX) -o $@ $(filter-out Makefile,$^) - -$(ONCEONLY): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< - -$(UNOPTIMIZED): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< - -$(OPTIMIZED): %.o: %.cpp - $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< - \ No newline at end of file diff --git a/src/main/resources/chisel3/Makefile b/src/main/resources/chisel3/Makefile new file mode 100644 index 00000000..221179a3 --- /dev/null +++ b/src/main/resources/chisel3/Makefile @@ -0,0 +1,35 @@ +# Chisel parallel make template. + +HFILES = @HFILES@ +ONCEONLY = @ONCEONLY@ +UNOPTIMIZED = @UNOPTIMIZED@ +OPTIMIZED = @OPTIMIZED@ + +EXEC = @EXEC@ +OPTIM0 = @OPTIM0@ +OPTIM1 = @OPTIM1@ +OPTIM2 = @OPTIM2@ +CPPFLAGS = @CPPFLAGS@ +CXXFLAGS = @CXXFLAGS@ +LDFLAGS = @LDFLAGS@ +CXX = @CXX@ + +default: $(EXEC) + +clean: + $(RM) $(EXEC) $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) + +$(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED): $(HFILES) + +$(EXEC): $(ONCEONLY) $(UNOPTIMIZED) $(OPTIMIZED) Makefile + $(CXX) -o $@ $(filter-out Makefile,$^) + +$(ONCEONLY): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM0) $(CPPFLAGS) $(CXXFLAGS) $< + +$(UNOPTIMIZED): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM1) $(CPPFLAGS) $(CXXFLAGS) $< + +$(OPTIMIZED): %.o: %.cpp + $(CXX) -c -o $@ $(OPTIM2) $(CPPFLAGS) $(CXXFLAGS) $< + \ No newline at end of file diff --git a/src/main/resources/chisel3/top.cpp b/src/main/resources/chisel3/top.cpp new file mode 100644 index 00000000..4e9c1433 --- /dev/null +++ b/src/main/resources/chisel3/top.cpp @@ -0,0 +1,95 @@ +#include +#include + +#if VM_TRACE +# include // Trace file format header +#endif + +// Override Verilator definition so first $finish ends simulation +// Note: VL_USER_FINISH needs to be defined when compiling Verilator code +void vl_finish(const char* filename, int linenum, const char* hier) { + Verilated::flushCall(); + exit(0); +} + +using namespace std; + +//VGCDTester *top; +TOP_TYPE *top; + +vluint64_t main_time = 0; // Current simulation time + // This is a 64-bit integer to reduce wrap over issues and + // allow modulus. You can also use a double, if you wish. + +double sc_time_stamp () { // Called by $time in Verilog + return main_time; // converts to double, to match + // what SystemC does +} + +// TODO Provide command-line options like vcd filename, timeout count, etc. +const long timeout = 100000000L; + +int main(int argc, char** argv) { + Verilated::commandArgs(argc, argv); // Remember args + top = new TOP_TYPE; + +#if VM_TRACE // If verilator was invoked with --trace + Verilated::traceEverOn(true); // Verilator must compute traced signals + VL_PRINTF("Enabling waves...\n"); + VerilatedVcdC* tfp = new VerilatedVcdC; + top->trace (tfp, 99); // Trace 99 levels of hierarchy + tfp->open ("dump.vcd"); // Open the dump file +#endif + + + top->reset = 1; + + cout << "Starting simulation!\n"; + + while (!Verilated::gotFinish() && main_time < timeout) { + if (main_time > 10) { + top->reset = 0; // Deassert reset + } + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + + if (main_time >= timeout) { + cout << "Simulation terminated by timeout at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + return -1; + } else { + cout << "Simulation completed at time " << main_time << + " (cycle " << main_time / 10 << ")"<< endl; + } + + // Run for 10 more clocks + vluint64_t end_time = main_time + 100; + while (main_time < end_time) { + if ((main_time % 10) == 1) { + top->clock = 1; // Toggle clock + } + if ((main_time % 10) == 6) { + top->clock = 0; + } + top->eval(); // Evaluate model +#if VM_TRACE + if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp +#endif + main_time++; // Time passes... + } + +#if VM_TRACE + if (tfp) tfp->close(); +#endif +} + diff --git a/src/main/resources/top.cpp b/src/main/resources/top.cpp deleted file mode 100644 index 4e9c1433..00000000 --- a/src/main/resources/top.cpp +++ /dev/null @@ -1,95 +0,0 @@ -#include -#include - -#if VM_TRACE -# include // Trace file format header -#endif - -// Override Verilator definition so first $finish ends simulation -// Note: VL_USER_FINISH needs to be defined when compiling Verilator code -void vl_finish(const char* filename, int linenum, const char* hier) { - Verilated::flushCall(); - exit(0); -} - -using namespace std; - -//VGCDTester *top; -TOP_TYPE *top; - -vluint64_t main_time = 0; // Current simulation time - // This is a 64-bit integer to reduce wrap over issues and - // allow modulus. You can also use a double, if you wish. - -double sc_time_stamp () { // Called by $time in Verilog - return main_time; // converts to double, to match - // what SystemC does -} - -// TODO Provide command-line options like vcd filename, timeout count, etc. -const long timeout = 100000000L; - -int main(int argc, char** argv) { - Verilated::commandArgs(argc, argv); // Remember args - top = new TOP_TYPE; - -#if VM_TRACE // If verilator was invoked with --trace - Verilated::traceEverOn(true); // Verilator must compute traced signals - VL_PRINTF("Enabling waves...\n"); - VerilatedVcdC* tfp = new VerilatedVcdC; - top->trace (tfp, 99); // Trace 99 levels of hierarchy - tfp->open ("dump.vcd"); // Open the dump file -#endif - - - top->reset = 1; - - cout << "Starting simulation!\n"; - - while (!Verilated::gotFinish() && main_time < timeout) { - if (main_time > 10) { - top->reset = 0; // Deassert reset - } - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - - if (main_time >= timeout) { - cout << "Simulation terminated by timeout at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - return -1; - } else { - cout << "Simulation completed at time " << main_time << - " (cycle " << main_time / 10 << ")"<< endl; - } - - // Run for 10 more clocks - vluint64_t end_time = main_time + 100; - while (main_time < end_time) { - if ((main_time % 10) == 1) { - top->clock = 1; // Toggle clock - } - if ((main_time % 10) == 6) { - top->clock = 0; - } - top->eval(); // Evaluate model -#if VM_TRACE - if (tfp) tfp->dump (main_time); // Create waveform trace for this timestamp -#endif - main_time++; // Time passes... - } - -#if VM_TRACE - if (tfp) tfp->close(); -#endif -} - diff --git a/src/main/scala/chisel3/testers/TesterDriver.scala b/src/main/scala/chisel3/testers/TesterDriver.scala index fd3ad9ba..fc71f2b0 100644 --- a/src/main/scala/chisel3/testers/TesterDriver.scala +++ b/src/main/scala/chisel3/testers/TesterDriver.scala @@ -28,7 +28,7 @@ object TesterDriver extends BackendCompilationUtilities { // Copy CPP harness and other Verilog sources from resources into files val cppHarness = new File(path, "top.cpp") - copyResourceToFile("/top.cpp", cppHarness) + copyResourceToFile("/chisel3/top.cpp", cppHarness) val additionalVFiles = additionalVResources.map((name: String) => { val mangledResourceName = name.replace("/", "_") val out = new File(path, mangledResourceName) diff --git a/src/test/resources/AnalogBlackBox.v b/src/test/resources/AnalogBlackBox.v deleted file mode 100644 index 79e74a13..00000000 --- a/src/test/resources/AnalogBlackBox.v +++ /dev/null @@ -1,27 +0,0 @@ - -module AnalogReaderBlackBox( - inout [31:0] bus, - output [31:0] out -); - assign bus = 32'dz; - assign out = bus; -endmodule - -module AnalogWriterBlackBox( - inout [31:0] bus, - input [31:0] in -); - assign bus = in; -endmodule - -module AnalogBlackBox #( - parameter index=0 -) ( - inout [31:0] bus, - input port_0_in_valid, - input [31:0] port_0_in_bits, - output [31:0] port_0_out -); - assign port_0_out = bus; - assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ; -endmodule diff --git a/src/test/resources/BlackBoxTest.v b/src/test/resources/BlackBoxTest.v deleted file mode 100644 index f88fb4ee..00000000 --- a/src/test/resources/BlackBoxTest.v +++ /dev/null @@ -1,67 +0,0 @@ -module BlackBoxInverter( - input [0:0] in, - output [0:0] out -); - assign out = !in; -endmodule - -module BlackBoxPassthrough( - input [0:0] in, - output [0:0] out -); - assign out = in; -endmodule - -module BlackBoxMinus( - input [15:0] in1, - input [15:0] in2, - output [15:0] out -); - assign out = in1 + in2; -endmodule - -module BlackBoxRegister( - input [0:0] clock, - input [0:0] in, - output [0:0] out -); - reg [0:0] register; - always @(posedge clock) begin - register <= in; - end - assign out = register; -endmodule - -module BlackBoxConstant #( - parameter int WIDTH=1, - parameter int VALUE=1 -) ( - output [WIDTH-1:0] out -); - assign out = VALUE; -endmodule - -module BlackBoxStringParam #( - parameter string STRING = "zero" -) ( - output [31:0] out -); - assign out = (STRING == "one" )? 1 : - (STRING == "two" )? 2 : 0; -endmodule - -module BlackBoxRealParam #( - parameter real REAL = 0.0 -) ( - output [63:0] out -); - assign out = $realtobits(REAL); -endmodule - -module BlackBoxTypeParam #( - parameter type T = bit -) ( - output T out -); - assign out = 32'hdeadbeef; -endmodule diff --git a/src/test/resources/VerilogVendingMachine.v b/src/test/resources/VerilogVendingMachine.v deleted file mode 100644 index c01259bd..00000000 --- a/src/test/resources/VerilogVendingMachine.v +++ /dev/null @@ -1,44 +0,0 @@ -// See LICENSE for license details. - -// A simple Verilog FSM vending machine implementation -module VerilogVendingMachine( - input clock, - input reset, - input nickel, - input dime, - output dispense -); - parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4; - reg [2:0] state; - wire [2:0] next_state; - - assign dispense = (state == sOk) ? 1'd1 : 1'd0; - - always @(*) begin - case (state) - sIdle: if (nickel) next_state <= s5; - else if (dime) next_state <= s10; - else next_state <= state; - s5: if (nickel) next_state <= s10; - else if (dime) next_state <= s15; - else next_state <= state; - s10: if (nickel) next_state <= s15; - else if (dime) next_state <= sOk; - else next_state <= state; - s15: if (nickel) next_state <= sOk; - else if (dime) next_state <= sOk; - else next_state <= state; - sOk: next_state <= sIdle; - endcase - end - - // Go to next state - always @(posedge clock) begin - if (reset) begin - state <= sIdle; - end else begin - state <= next_state; - end - end -endmodule - diff --git a/src/test/resources/chisel3/AnalogBlackBox.v b/src/test/resources/chisel3/AnalogBlackBox.v new file mode 100644 index 00000000..79e74a13 --- /dev/null +++ b/src/test/resources/chisel3/AnalogBlackBox.v @@ -0,0 +1,27 @@ + +module AnalogReaderBlackBox( + inout [31:0] bus, + output [31:0] out +); + assign bus = 32'dz; + assign out = bus; +endmodule + +module AnalogWriterBlackBox( + inout [31:0] bus, + input [31:0] in +); + assign bus = in; +endmodule + +module AnalogBlackBox #( + parameter index=0 +) ( + inout [31:0] bus, + input port_0_in_valid, + input [31:0] port_0_in_bits, + output [31:0] port_0_out +); + assign port_0_out = bus; + assign bus = (port_0_in_valid)? port_0_in_bits + index : 32'dZ; +endmodule diff --git a/src/test/resources/chisel3/BlackBoxTest.v b/src/test/resources/chisel3/BlackBoxTest.v new file mode 100644 index 00000000..f88fb4ee --- /dev/null +++ b/src/test/resources/chisel3/BlackBoxTest.v @@ -0,0 +1,67 @@ +module BlackBoxInverter( + input [0:0] in, + output [0:0] out +); + assign out = !in; +endmodule + +module BlackBoxPassthrough( + input [0:0] in, + output [0:0] out +); + assign out = in; +endmodule + +module BlackBoxMinus( + input [15:0] in1, + input [15:0] in2, + output [15:0] out +); + assign out = in1 + in2; +endmodule + +module BlackBoxRegister( + input [0:0] clock, + input [0:0] in, + output [0:0] out +); + reg [0:0] register; + always @(posedge clock) begin + register <= in; + end + assign out = register; +endmodule + +module BlackBoxConstant #( + parameter int WIDTH=1, + parameter int VALUE=1 +) ( + output [WIDTH-1:0] out +); + assign out = VALUE; +endmodule + +module BlackBoxStringParam #( + parameter string STRING = "zero" +) ( + output [31:0] out +); + assign out = (STRING == "one" )? 1 : + (STRING == "two" )? 2 : 0; +endmodule + +module BlackBoxRealParam #( + parameter real REAL = 0.0 +) ( + output [63:0] out +); + assign out = $realtobits(REAL); +endmodule + +module BlackBoxTypeParam #( + parameter type T = bit +) ( + output T out +); + assign out = 32'hdeadbeef; +endmodule diff --git a/src/test/resources/chisel3/VerilogVendingMachine.v b/src/test/resources/chisel3/VerilogVendingMachine.v new file mode 100644 index 00000000..c01259bd --- /dev/null +++ b/src/test/resources/chisel3/VerilogVendingMachine.v @@ -0,0 +1,44 @@ +// See LICENSE for license details. + +// A simple Verilog FSM vending machine implementation +module VerilogVendingMachine( + input clock, + input reset, + input nickel, + input dime, + output dispense +); + parameter sIdle = 3'd0, s5 = 3'd1, s10 = 3'd2, s15 = 3'd3, sOk = 3'd4; + reg [2:0] state; + wire [2:0] next_state; + + assign dispense = (state == sOk) ? 1'd1 : 1'd0; + + always @(*) begin + case (state) + sIdle: if (nickel) next_state <= s5; + else if (dime) next_state <= s10; + else next_state <= state; + s5: if (nickel) next_state <= s10; + else if (dime) next_state <= s15; + else next_state <= state; + s10: if (nickel) next_state <= s15; + else if (dime) next_state <= sOk; + else next_state <= state; + s15: if (nickel) next_state <= sOk; + else if (dime) next_state <= sOk; + else next_state <= state; + sOk: next_state <= sIdle; + endcase + end + + // Go to next state + always @(posedge clock) begin + if (reset) begin + state <= sIdle; + end else begin + state <= next_state; + end + end +endmodule + diff --git a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala index de717c4f..952d3872 100644 --- a/src/test/scala/chiselTests/AnalogIntegrationSpec.scala +++ b/src/test/scala/chiselTests/AnalogIntegrationSpec.scala @@ -126,10 +126,10 @@ class AnalogIntegrationTester(mod: => AnalogDUTModule) extends BasicTester { class AnalogIntegrationSpec extends ChiselFlatSpec { behavior of "Verilator" it should "support simple bidirectional wires" in { - assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/AnalogBlackBox.v")) + assertTesterPasses(new AnalogIntegrationTester(new AnalogSmallDUT), Seq("/chisel3/AnalogBlackBox.v")) } // Use this test once Verilator supports alias ignore should "support arbitrary bidirectional wires" in { - assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/AnalogBlackBox.v")) + assertTesterPasses(new AnalogIntegrationTester(new AnalogDUT), Seq("/chisel3/AnalogBlackBox.v")) } } diff --git a/src/test/scala/chiselTests/AnalogSpec.scala b/src/test/scala/chiselTests/AnalogSpec.scala index 5db9ab53..c2dee4a9 100644 --- a/src/test/scala/chiselTests/AnalogSpec.scala +++ b/src/test/scala/chiselTests/AnalogSpec.scala @@ -130,7 +130,7 @@ class AnalogSpec extends ChiselFlatSpec { val mod = Module(new AnalogReaderBlackBox) mod.io.bus <> writer.io.bus check(mod) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } it should "error if any bulk connected more than once" in { @@ -149,7 +149,7 @@ class AnalogSpec extends ChiselFlatSpec { val mods = Seq.fill(2)(Module(new AnalogReaderBlackBox)) attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus) mods.foreach(check(_)) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } it should "work with 3 blackboxes separately attached via a wire" in { @@ -160,7 +160,7 @@ class AnalogSpec extends ChiselFlatSpec { attach(busWire, mods(0).io.bus) attach(mods(1).io.bus, busWire) mods.foreach(check(_)) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } // This does not currently work in Verilator unless Firrtl does constant prop and dead code @@ -173,7 +173,7 @@ class AnalogSpec extends ChiselFlatSpec { attach(busWire(1), mod.io.bus) attach(busWire(0), busWire(1)) check(mod) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } it should "work with blackboxes at different levels of the module hierarchy" in { @@ -182,7 +182,7 @@ class AnalogSpec extends ChiselFlatSpec { val busWire = Wire(writer.io.bus) attach(writer.io.bus, mods(0).io.bus, mods(1).io.bus) mods.foreach(check(_)) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } // This does not currently work in Verilator, but does work in VCS @@ -193,7 +193,7 @@ class AnalogSpec extends ChiselFlatSpec { connector.io.bus1 <> writer.io.bus reader.io.bus <> connector.io.bus2 check(reader) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } it should "NOT support conditional connection of analog types" in { @@ -204,7 +204,7 @@ class AnalogSpec extends ChiselFlatSpec { mod.io.bus <> writer.io.bus } check(mod) - }, Seq("/AnalogBlackBox.v")) + }, Seq("/chisel3/AnalogBlackBox.v")) } } } diff --git a/src/test/scala/chiselTests/BlackBox.scala b/src/test/scala/chiselTests/BlackBox.scala index 164c7b6f..b3791fd9 100644 --- a/src/test/scala/chiselTests/BlackBox.scala +++ b/src/test/scala/chiselTests/BlackBox.scala @@ -138,18 +138,18 @@ class BlackBoxWithParamsTester extends BasicTester { class BlackBoxSpec extends ChiselFlatSpec { "A BlackBoxed inverter" should "work" in { assertTesterPasses({ new BlackBoxTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } "Multiple BlackBoxes" should "work" in { assertTesterPasses({ new MultiBlackBoxTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } "A BlackBoxed register" should "work" in { assertTesterPasses({ new BlackBoxWithClockTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } "BlackBoxes with parameters" should "work" in { assertTesterPasses({ new BlackBoxWithParamsTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } } diff --git a/src/test/scala/chiselTests/BlackBoxImpl.scala b/src/test/scala/chiselTests/BlackBoxImpl.scala index 11d59fe9..a6784909 100644 --- a/src/test/scala/chiselTests/BlackBoxImpl.scala +++ b/src/test/scala/chiselTests/BlackBoxImpl.scala @@ -47,7 +47,7 @@ class BlackBoxMinus extends HasBlackBoxResource { val in2 = Input(UInt(16.W)) val out = Output(UInt(16.W)) }) - setResource("/BlackBoxTest.v") + setResource("/chisel3/BlackBoxTest.v") } class UsesBlackBoxMinusViaResource extends Module { diff --git a/src/test/scala/chiselTests/ExtModule.scala b/src/test/scala/chiselTests/ExtModule.scala index f8927b9f..6bffa333 100644 --- a/src/test/scala/chiselTests/ExtModule.scala +++ b/src/test/scala/chiselTests/ExtModule.scala @@ -62,10 +62,10 @@ class MultiExtModuleTester extends BasicTester { class ExtModuleSpec extends ChiselFlatSpec { "A ExtModule inverter" should "work" in { assertTesterPasses({ new ExtModuleTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } "Multiple ExtModules" should "work" in { assertTesterPasses({ new MultiExtModuleTester }, - Seq("/BlackBoxTest.v")) + Seq("/chisel3/BlackBoxTest.v")) } } diff --git a/src/test/scala/examples/SimpleVendingMachine.scala b/src/test/scala/examples/SimpleVendingMachine.scala index e8ca7c77..a34a7051 100644 --- a/src/test/scala/examples/SimpleVendingMachine.scala +++ b/src/test/scala/examples/SimpleVendingMachine.scala @@ -90,6 +90,6 @@ class SimpleVendingMachineSpec extends ChiselFlatSpec { } "An Verilog implementation of a vending machine" should "work" in { assertTesterPasses(new SimpleVendingMachineTester(new VerilogVendingMachineWrapper), - List("/VerilogVendingMachine.v")) + List("/chisel3/VerilogVendingMachine.v")) } } -- cgit v1.2.3