From ce6ad2116284291df24b5c8a2536deaad0ec7f04 Mon Sep 17 00:00:00 2001
From: ducky
Date: Tue, 10 May 2016 14:58:14 -0700
Subject: Move emit out of IR

---
 chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala | 4 ++++
 chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala      | 4 +---
 src/main/scala/Chisel/Driver.scala                                 | 4 ++--
 3 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
index b690d974..34547503 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/Emitter.scala
@@ -3,6 +3,10 @@
 package Chisel.internal.firrtl
 import Chisel._
 
+private[Chisel] object Emitter {
+  def emit(circuit: Circuit): String = new Emitter(circuit).toString
+}
+
 private class Emitter(circuit: Circuit) {
   override def toString: String = res.toString
 
diff --git a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
index 1e06a663..91dcf5d2 100644
--- a/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
+++ b/chiselFrontend/src/main/scala/Chisel/internal/firrtl/IR.scala
@@ -182,6 +182,4 @@ case class Printf(clk: Arg, formatIn: String, ids: Seq[Arg]) extends Command {
   }
 }
 
-case class Circuit(name: String, components: Seq[Component]) {
-  def emit: String = new Emitter(this).toString
-}
+case class Circuit(name: String, components: Seq[Component])
diff --git a/src/main/scala/Chisel/Driver.scala b/src/main/scala/Chisel/Driver.scala
index 830bc005..d5952834 100644
--- a/src/main/scala/Chisel/Driver.scala
+++ b/src/main/scala/Chisel/Driver.scala
@@ -110,12 +110,12 @@ object Driver extends BackendCompilationUtilities {
     */
   def elaborate[T <: Module](gen: () => T): Circuit = Builder.build(Module(gen()))
 
-  def emit[T <: Module](gen: () => T): String = elaborate(gen).emit
+  def emit[T <: Module](gen: () => T): String = Emitter.emit(elaborate(gen))
 
   def dumpFirrtl(ir: Circuit, optName: Option[File]): File = {
     val f = optName.getOrElse(new File(ir.name + ".fir"))
     val w = new FileWriter(f)
-    w.write(ir.emit)
+    w.write(Emitter.emit(ir))
     w.close()
     f
   }
-- 
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