From 7fc39a02a806bfb74c78147203815f2e2b85b765 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Sun, 24 Dec 2023 13:13:20 -0800
Subject: Add the type aggregation problem

---
 AbstractModule.scala                          | 26 +++++++++++---------------
 core/src/main/scala/chisel3/MetaConnect.scala | 19 ++-----------------
 2 files changed, 13 insertions(+), 32 deletions(-)

diff --git a/AbstractModule.scala b/AbstractModule.scala
index 10aca713..e179c684 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -4,6 +4,9 @@ import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.MetaConnect._
 
+class AbstractModule[T <: Data](params: T) {
+  val ioNode = IO(params)
+}
 
 object TypeArithmetic {
   implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
@@ -12,27 +15,20 @@ object TypeArithmetic {
 
 case class SomeTypeContainer(w: Int) extends UInt(w.W)
 
-class AbstractModule[T <: Data](params: T) extends Module[T] {
-  val node = IO(params)
-}
-
 class AbstractModuleContainer extends Module {
-  val mod1 = Module(new AbstractModule[UInt](Input(UInt(4.W))))
-  val mod2 = Module(new AbstractModule[UInt](Output(UInt(8.W))))
-
-  val tc = SomeTypeContainer(16)
-  val mod3 = Module(new AbstractModule[tc.type](Output(tc)))
+  val mod1 = new AbstractModule[UInt](Input(UInt(4.W)))
+  val mod2 = new AbstractModule[UInt](Output(UInt(8.W)))
+  val mod3 = new AbstractModule[SomeTypeContainer](Output(SomeTypeContainer(16)))
 
   import TypeArithmetic._
-  mod3.node.makeConnection(mod1.node.makeConnection(mod2.node))
-
-  // goal is to get this to work:
-  // mod1.node := mod2.node := mod3.node
+  val typeA = mod1.ioNode.makeConnection(mod2.ioNode)
+  val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
+  // need to create versions of mods1-3 with these new type params
+  // similar to log aggregation writer monad? but more like type aggregation
 }
 
 object main {
   def main(args: Array[String]): Unit = {
-    // println(getVerilogString(new Example))
-    println(chisel3.stage.ChiselStage.emitVerilog(new AbstractModuleContainer))
+    println(chisel3.stage.ChiselStage.emitChirrtl(new AbstractModuleContainer))
   }
 }
diff --git a/core/src/main/scala/chisel3/MetaConnect.scala b/core/src/main/scala/chisel3/MetaConnect.scala
index ebdff5f8..0f338e6c 100644
--- a/core/src/main/scala/chisel3/MetaConnect.scala
+++ b/core/src/main/scala/chisel3/MetaConnect.scala
@@ -2,23 +2,8 @@ package chisel3
 
 object MetaConnect {
   implicit class Connection[A](that: A) {
-    def makeConnection[B](me: B)(implicit f: A => B => A): Unit = {
-      println(me, that)
-      (me, that) match {
-        case (a: Data, b: Data) => {
-          if (a == b) {
-            a.connect(b)
-          }
-          else {
-
-          }
-        }
-        case (_, _) => 
-      }
+    def makeConnection[B, C](me: B)(implicit f: A => B => C): C = {
+      f(that)(me)
     }
-    // def makeConnection[B](me: B): Unit = {
-
-    // }
-    // def :=(a: Data, b: Data) = a.connect(b)
   }
 }
-- 
cgit v1.2.3