From 7a3a5a07e9e340e11f8b7cb6a53c1f52f4e4d3a1 Mon Sep 17 00:00:00 2001
From: Aditya Naik
Date: Tue, 2 Jan 2024 11:29:49 -0800
Subject: Add AbstractInterface and AbstractModule

---
 AbstractModule.scala                             | 20 +++++++++++---------
 core/src/main/scala/chisel3/AbstractModule.scala | 22 ++++++++++++++++++++++
 2 files changed, 33 insertions(+), 9 deletions(-)
 create mode 100644 core/src/main/scala/chisel3/AbstractModule.scala

diff --git a/AbstractModule.scala b/AbstractModule.scala
index e179c684..e7d7a5e0 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -4,10 +4,6 @@ import chisel3._
 import chisel3.stage.ChiselStage
 import chisel3.MetaConnect._
 
-class AbstractModule[T <: Data](params: T) {
-  val ioNode = IO(params)
-}
-
 object TypeArithmetic {
   implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
   implicit val f2: SomeTypeContainer => Unit => SomeTypeContainer = (a: SomeTypeContainer) => (b: Unit) => a
@@ -15,20 +11,26 @@ object TypeArithmetic {
 
 case class SomeTypeContainer(w: Int) extends UInt(w.W)
 
-class AbstractModuleContainer extends Module {
-  val mod1 = new AbstractModule[UInt](Input(UInt(4.W)))
-  val mod2 = new AbstractModule[UInt](Output(UInt(8.W)))
-  val mod3 = new AbstractModule[SomeTypeContainer](Output(SomeTypeContainer(16)))
+class AbstractModuleContainer extends AbstractModule({
+  val mod1 = new AbstractInterface[UInt](Input(UInt(4.W)))
+  val mod2 = new AbstractInterface[UInt](Output(UInt(8.W)))
+  val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16)))
 
   import TypeArithmetic._
   val typeA = mod1.ioNode.makeConnection(mod2.ioNode)
   val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
+  // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
   // need to create versions of mods1-3 with these new type params
   // similar to log aggregation writer monad? but more like type aggregation
+  mod1
+})
+
+class LowerableModule extends Module {
+  val innerModule = Module(new AbstractModuleContainer)
 }
 
 object main {
   def main(args: Array[String]): Unit = {
-    println(chisel3.stage.ChiselStage.emitChirrtl(new AbstractModuleContainer))
+    println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule))
   }
 }
diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
new file mode 100644
index 00000000..e054e537
--- /dev/null
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -0,0 +1,22 @@
+package chisel3
+
+import scala.collection.immutable.ListMap
+import scala.collection.mutable.{ArrayBuffer, HashMap}
+import scala.language.experimental.macros
+
+import chisel3.internal._
+import chisel3.internal.Builder._
+import chisel3.internal.firrtl._
+import chisel3.experimental.BaseModule
+
+class AbstractInterface[T <: Data](params: T) {
+  val ioNode = IO(params)
+}
+
+/**
+  A module that uses types from its metaconnects to type its IOs. 
+  */
+class AbstractModule(iface: AbstractInterface[_]*) extends BaseModule {
+  def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
+  def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
+}
-- 
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