From 70b59235cfef3c0391ddee0e406bc806e11a1557 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Wed, 25 Sep 2019 15:22:11 -0400 Subject: Use full URL links for images Signed-off-by: Schuyler Eldridge --- README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/README.md b/README.md index 13e38610..fb91897f 100644 --- a/README.md +++ b/README.md @@ -18,7 +18,7 @@ Chisel is powered by [FIRRTL (Flexible Intermediate Representation for RTL)](htt Consider an FIR filter that implements a convolution operation, as depicted in this block diagram: - + While Chisel provides similar base primitives as synthesizable Verilog, and *could* be used as such: @@ -112,7 +112,7 @@ If you are migrating from Chisel2, see [the migration guide on the wiki](https:/ ### Data Types Overview These are the base data types for defining circuit wires (abstract types which may not be instantiated are greyed out): -![Image](doc/images/type_hierarchy.png?raw=true) +![Image](https://raw.githubusercontent.com/freechipsproject/chisel3/master/doc/images/type_hierarchy.svg?sanitize=true) ## Developer Documentation This section describes how to get started developing Chisel itself, including how to test your version locally against other projects that pull in Chisel using [sbt's managed dependencies](https://www.scala-sbt.org/1.x/docs/Library-Dependencies.html). -- cgit v1.2.3