From 6043ede715a44992975e60990fd2924b1ea6896a Mon Sep 17 00:00:00 2001 From: chick Date: Thu, 12 Dec 2019 12:06:15 -0800 Subject: Fixed problem creating Interval literals with full ranges - boundary testing was not taking binary point into account correctly - add tests to show where things work and where they are supposed to fail --- chiselFrontend/src/main/scala/chisel3/Bits.scala | 10 +++--- src/test/scala/chiselTests/IntervalSpec.scala | 44 +++++++++++++++++++++++- 2 files changed, 48 insertions(+), 6 deletions(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Bits.scala b/chiselFrontend/src/main/scala/chisel3/Bits.scala index 28d1690d..af13ee44 100644 --- a/chiselFrontend/src/main/scala/chisel3/Bits.scala +++ b/chiselFrontend/src/main/scala/chisel3/Bits.scala @@ -2162,16 +2162,16 @@ package experimental { protected[chisel3] def Lit(value: BigInt, range: IntervalRange): Interval = { val lit = IntervalLit(value, range.getWidth, range.binaryPoint) - val bigDecimal = BigDecimal(value) + val bigDecimal = BigDecimal(value) / (1 << lit.binaryPoint.get) val inRange = (range.lowerBound, range.upperBound) match { case (firrtlir.Closed(l), firrtlir.Closed(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Closed(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Open(l), firrtlir.Closed(u)) => l <= bigDecimal && bigDecimal <= u - case (firrtlir.Open(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal <= u + case (firrtlir.Closed(l), firrtlir.Open(u)) => l <= bigDecimal && bigDecimal < u + case (firrtlir.Open(l), firrtlir.Closed(u)) => l < bigDecimal && bigDecimal <= u + case (firrtlir.Open(l), firrtlir.Open(u)) => l < bigDecimal && bigDecimal < u } if(! inRange) { throw new ChiselException( - s"Error literal interval value $value is not contained in specified range $range" + s"Error literal interval value $bigDecimal is not contained in specified range $range" ) } val result = Interval(range) diff --git a/src/test/scala/chiselTests/IntervalSpec.scala b/src/test/scala/chiselTests/IntervalSpec.scala index 863771a3..1e56d8a3 100644 --- a/src/test/scala/chiselTests/IntervalSpec.scala +++ b/src/test/scala/chiselTests/IntervalSpec.scala @@ -456,12 +456,54 @@ class IntervalSpec extends FreeSpec with Matchers with ChiselRunners { () => new BasicTester { val x = 5.I(range"[0,4]") - } + } ).elaborate } } } + "Interval literals creation handles edge cases" - { + "value at closed boundaries works" in { + val inputRange = range"[-6, 6].2" + val in1 = (-6.0).I(inputRange) + val in2 = 6.0.I(inputRange) + BigDecimal(in1.litValue()) / (1 << inputRange.binaryPoint.get) should be (-6) + BigDecimal(in2.litValue()) / (1 << inputRange.binaryPoint.get) should be (6) + intercept[ChiselException] { + (-6.25).I(inputRange) + } + intercept[ChiselException] { + (6.25).I(inputRange) + } + } + "value at open boundaries works" in { + val inputRange = range"(-6, 6).2" + val in1 = (-5.75).I(inputRange) + val in2 = 5.75.I(inputRange) + BigDecimal(in1.litValue()) / (1 << inputRange.binaryPoint.get) should be (-5.75) + BigDecimal(in2.litValue()) / (1 << inputRange.binaryPoint.get) should be (5.75) + intercept[ChiselException] { + (-6.0).I(inputRange) + } + intercept[ChiselException] { + (6.0).I(inputRange) + } + } + "values not precisely at open boundaries works but are converted to nearest match" in { + val inputRange = range"(-6, 6).2" + val in1 = (-5.95).I(inputRange) + val in2 = 5.95.I(inputRange) + BigDecimal(in1.litValue()) / (1 << inputRange.binaryPoint.get) should be (-5.75) + BigDecimal(in2.litValue()) / (1 << inputRange.binaryPoint.get) should be (5.75) + intercept[ChiselException] { + (-6.1).I(inputRange) + } + intercept[ChiselException] { + (6.1).I(inputRange) + } + } + } + "Let's take a look at the results of squeeze over small range" in { assertTesterPasses { new ClipSqueezeWrapDemo( -- cgit v1.2.3 From 4ef91c4c43d6ab808e79edd239062f919a5bbbe3 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 16 Dec 2019 15:07:55 -0500 Subject: Remove unused WriteEmitted phase (#1273) This removes a dead line where a WriteEmitted phase is constructed. Signed-off-by: Schuyler Eldridge --- src/main/scala/chisel3/stage/package.scala | 1 - 1 file changed, 1 deletion(-) diff --git a/src/main/scala/chisel3/stage/package.scala b/src/main/scala/chisel3/stage/package.scala index 67d38ae7..57766be6 100644 --- a/src/main/scala/chisel3/stage/package.scala +++ b/src/main/scala/chisel3/stage/package.scala @@ -28,7 +28,6 @@ package object stage { private[chisel3] implicit object ChiselExecutionResultView extends OptionsView[ChiselExecutionResult] { - lazy val dummyWriteEmitted = new firrtl.stage.phases.WriteEmitted lazy val dummyConvert = new Convert lazy val dummyEmitter = new Emitter -- cgit v1.2.3 From 98a6710cc0447d79cbd12271ea450c70e619b6f8 Mon Sep 17 00:00:00 2001 From: Jim Lawson Date: Tue, 17 Dec 2019 12:41:36 -0800 Subject: Band aid until litOption is implemented for Aggregates. (#1277) This is just a band aid until an Aggregate `isLit()` method (for which work has begun) is implemented.--- chiselFrontend/src/main/scala/chisel3/Aggregate.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala index 42b40ed9..8141fdba 100644 --- a/chiselFrontend/src/main/scala/chisel3/Aggregate.scala +++ b/chiselFrontend/src/main/scala/chisel3/Aggregate.scala @@ -43,7 +43,7 @@ sealed abstract class Aggregate extends Data { } } - override def litOption: Option[BigInt] = ??? // TODO implement me + override def litOption: Option[BigInt] = None // TODO implement me /** Returns a Seq of the immediate contents of this Aggregate, in order. */ -- cgit v1.2.3 From c720c99a75f565c8b4fbc7147d7b9daee9123d10 Mon Sep 17 00:00:00 2001 From: chick Date: Wed, 18 Dec 2019 10:04:13 -0800 Subject: BitPat supports whitespace and underscores, presumably for human readability. The BitPat.parse factory though did not remove these from the returned count. This fixes that adds whitespace and underscores to the unit tests This is an updated vesion of Chisel PR #1069 --- src/main/scala/chisel3/util/BitPat.scala | 9 ++++++--- src/test/scala/chiselTests/Decoder.scala | 14 ++++++++++++-- 2 files changed, 18 insertions(+), 5 deletions(-) diff --git a/src/main/scala/chisel3/util/BitPat.scala b/src/main/scala/chisel3/util/BitPat.scala index 83475d1b..7c0abdb2 100644 --- a/src/main/scala/chisel3/util/BitPat.scala +++ b/src/main/scala/chisel3/util/BitPat.scala @@ -14,7 +14,7 @@ object BitPat { * @return bits the literal value, with don't cares being 0 * @return mask the mask bits, with don't cares being 0 and cares being 1 * @return width the number of bits in the literal, including values and - * don't cares. + * don't cares, but not including the white space and underscores */ private def parse(x: String): (BigInt, BigInt, Int) = { // Notes: @@ -25,14 +25,17 @@ object BitPat { require(x.head == 'b', "BitPats must be in binary and be prefixed with 'b'") var bits = BigInt(0) var mask = BigInt(0) + var count = 0 for (d <- x.tail) { - if (d != '_') { + if (! (d == '_' || d.isWhitespace)) { require("01?".contains(d), "Literal: " + x + " contains illegal character: " + d) mask = (mask << 1) + (if (d == '?') 0 else 1) bits = (bits << 1) + (if (d == '1') 1 else 0) + count += 1 } } - (bits, mask, x.length - 1) + + (bits, mask, count) } /** Creates a [[BitPat]] literal from a string. diff --git a/src/test/scala/chiselTests/Decoder.scala b/src/test/scala/chiselTests/Decoder.scala index 59ad6324..44cacccc 100644 --- a/src/test/scala/chiselTests/Decoder.scala +++ b/src/test/scala/chiselTests/Decoder.scala @@ -36,8 +36,18 @@ class DecoderSpec extends ChiselPropSpec { val bitpatPair = for(seed <- Arbitrary.arbitrary[Int]) yield { val rnd = new scala.util.Random(seed) val bs = seed.toBinaryString - val bp = bs.map(if(rnd.nextBoolean) _ else "?").mkString - ("b" + bs, "b" + bp) + val bp = bs.map(if(rnd.nextBoolean) _ else "?") + + // The following randomly throws in white space and underscores which are legal and ignored. + val bpp = bp.map { a => + if (rnd.nextBoolean) { + a + } else { + a + (if (rnd.nextBoolean) "_" else " ") + } + }.mkString + + ("b" + bs, "b" + bpp) } private def nPairs(n: Int) = Gen.containerOfN[List, (String,String)](n,bitpatPair) -- cgit v1.2.3 From d4300b9deae6dde7ce0f314ea73a9ca4a1c3868c Mon Sep 17 00:00:00 2001 From: Leway Colin Date: Wed, 8 Jan 2020 06:25:29 +0800 Subject: Remove over design (#1237) Co-authored-by: Albert Magyar Co-authored-by: Chick Markley --- chiselFrontend/src/main/scala/chisel3/internal/Builder.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala index b5f617f0..c119315d 100644 --- a/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala +++ b/chiselFrontend/src/main/scala/chisel3/internal/Builder.scala @@ -18,7 +18,7 @@ private[chisel3] class Namespace(keywords: Set[String]) { names(keyword) = 1 private def rename(n: String): String = { - val index = names.getOrElse(n, 1L) + val index = names(n) val tryName = s"${n}_${index}" names(n) = index + 1 if (this contains tryName) rename(n) else tryName -- cgit v1.2.3 From 0a98a82c588882eb2905a5564792670c2cfaf858 Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Fri, 17 Jan 2020 15:52:57 -0800 Subject: Bugfix: Select.instances now works with blackboxes (#1303) --- src/main/scala/chisel3/aop/Select.scala | 7 +++++-- src/test/scala/chiselTests/aop/SelectSpec.scala | 16 +++++++++++++++- 2 files changed, 20 insertions(+), 3 deletions(-) diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala index 612cdcc7..390f82a5 100644 --- a/src/main/scala/chisel3/aop/Select.scala +++ b/src/main/scala/chisel3/aop/Select.scala @@ -80,8 +80,11 @@ object Select { */ def instances(module: BaseModule): Seq[BaseModule] = { check(module) - module._component.get.asInstanceOf[DefModule].commands.collect { - case i: DefInstance => i.id + module._component.get match { + case d: DefModule => d.commands.collect { + case i: DefInstance => i.id + } + case other => Nil } } diff --git a/src/test/scala/chiselTests/aop/SelectSpec.scala b/src/test/scala/chiselTests/aop/SelectSpec.scala index f3c756ab..80ab518f 100644 --- a/src/test/scala/chiselTests/aop/SelectSpec.scala +++ b/src/test/scala/chiselTests/aop/SelectSpec.scala @@ -7,7 +7,9 @@ import chiselTests.ChiselFlatSpec import chisel3._ import chisel3.aop.Select.{PredicatedConnect, When, WhenNot} import chisel3.aop.{Aspect, Select} -import firrtl.{AnnotationSeq} +import chisel3.experimental.ExtModule +import chisel3.stage.{ChiselGeneratorAnnotation, DesignAnnotation} +import firrtl.AnnotationSeq import scala.reflect.runtime.universe.TypeTag @@ -139,5 +141,17 @@ class SelectSpec extends ChiselFlatSpec { ) } + "Blackboxes" should "be supported in Select.instances" in { + class BB extends ExtModule { } + class Top extends RawModule { + val bb = Module(new BB) + } + val top = ChiselGeneratorAnnotation(() => { + new Top() + }).elaborate(1).asInstanceOf[DesignAnnotation[Top]].design + val bbs = Select.collectDeep(top) { case b: BB => b } + assert(bbs.size == 1) + } + } -- cgit v1.2.3 From c7715c160a0dd07765e736b813c8b6b26b27de28 Mon Sep 17 00:00:00 2001 From: Deborah Soung Date: Mon, 20 Jan 2020 16:48:31 -0800 Subject: specifying type of target field (#1305) --- src/main/scala/chisel3/stage/ChiselStage.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index 0a0cc47c..df23f97d 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -16,7 +16,7 @@ import java.io.{StringWriter, PrintWriter} class ChiselStage extends Stage with PreservesAll[Phase] { val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli - val targets = + val targets: Seq[PhaseManager.PhaseDependency] = Seq( classOf[chisel3.stage.phases.Checks], classOf[chisel3.stage.phases.Elaborate], classOf[chisel3.stage.phases.AddImplicitOutputFile], -- cgit v1.2.3